TLC320AD80 Datasheet, PDF (27/37 Pages) Texas Instruments – Audio Processor Subsystem

3.4 Timing Requirements, T_A = 25 °C, AV_DD = DV_DD = 5 V ± 5%, f_s = 48 kHz
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Input frequency,
MCLK1, MCLK2
4.096
18.432 MHz
fs
Audio sample rate
8
tsu1 Setup time, PCM data Relative to the rising edge of BCLK
th1 Hold time, PCM data Relative to the rising edge of BCLK
tsu2 Setup time, LRCLK
Relative to the rising edge of BCLK
th2 Hold time, LRCLK
Relative to the rising edge of BCLK
48 kHz
60 ns
0 ns
60 ns
0 ns
3.4.1 Serial PCM Data Port (see Figures 3–1 and 3–2)
tc(BCLK)
tr(BCLK)
tf(BCLK)
tsu(LRCLK)
th(LRCLK)
tsu(SDATA)
th(SDATA)
td(SDATA)
twL(BCLK)
twH(BCLK)
twL(MCLK)
twH(MCLK)
tr(MCLK)
tf(MCLK)
PARAMETER
Cycle time, BCLK
Rise time, BCLK
Fall time, BCLK
Setup time, LRCLK↓ before BCLK↑
Hold time, LRCLK↑ after BCLK↑
Setup time, SDATA before BCLK↑
Hold time, SDATA after BCLK↑
Delay time, SDATA valid after BCLK↓
Pulse duration, BCLK low
Pulse duration, BCLK high
Pulse duration, MCLK low
Pulse duration, MCLK high
Rise time, MCLK
Fall time, MCLK
MIN TYP
MAX
60
0
0
0
0
0
0
0
60
60
60
60
0
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.4.2 Serial Control Interface, T_A = 25°C, AV_DD = DV_DD = 5 V ± 5%, (see Figure 3–3)
DESCRIPTION
MIN TYP MAX UNITS
fSCLK
tc(SCLK)
twL(SCLK)
twH(SCLK)
tsu(CS)
th(CS)
tsu(CDIN)
th(CDIN)
td(CDOUT)
th(CDOUT)
tr(SCLK)
tf(SCLK)
Input frequency, SCLK
Cycle time, SCLK
Pulse width, SCLK low
Pulse width, SCLK high
Setup time, CS↓ before SCLK↓
Hold time, CS↑ after SCLK↑
Setup time, CDIN before SCLK↑
Hold time, CDIN after SCLK↑
Delay time, CDOUT after SCLK↓
Hold time, CDOUT after SCLK↓
Rise time, SCLK
Fall time, SCLK
3
MHz
333
ns
100
ns
100
ns
150
ns
150
ns
50
ns
50
ns
30
ns
5
ns
100
ns
100
ns
3–5