TLC320AD80 Datasheet, PDF (13/37 Pages) Texas Instruments – Audio Processor Subsystem

The external connections to this function allow for dc blocking capacitors to be included on the board, thus
eliminating dc offsets present on the source. A typical implementation would connect the output of the
analog multiplexer (EXT OUTL, EXT OUTR) to the input of this function.
The analog output multiplexer allows selection of the several analog sources input to the device. One of
these audio sources is the output of the DAC. The others are the output of the TV monaural decoder, either
of the two stereo analog inputs, or auxiliary mono input. Mono sources are sent to both right and left
channels. The output of this multiplexer provides stereo outputs on two terminals, each with 10 kΩ drive
capability. Both terminals are short-circuit protected.
The master clock for the device is derived from an external clock source. Control register 01h selects MCLK
1, or MCLK 2 to be the master clock source. This clock is then used to clock the DAC, the digital audio serial
ports, and the monural decoder, switched-capacitor filter. The serial ports can be selected independent form
the MCLK 1 and MCLK 2 selection. However, the clock rate of the selected clock source partly determines
the sampling rate of the device. Refer to Table 2–1, and the description of control register 00h.
The TLC320AD80 also provides an uncommitted 2:1 mono analog multiplexer. The inputs and outputs of
this device are connected to external terminals.
The voltage reference is used internally for the analog sections of the device. The external terminals must
be connected to decoupling capacitors. In addition, the reference terminals can be externally buffered for
use with external support circuitry.
2.1 Audio Input Ports
The audio inputs consist of: two digital serial interfaces, two stereo analog inputs, one analog TV baseband
audio input, and one mono analog input. The TV baseband audio input is a differential input. All other analog
inputs are single-ended.
The audio input is selected by programming control register 01h. Only one of these inputs is active at any
one time. The others are disabled. That is, if an analog input is selected, then the digital serial interfaces
are inactive.
The two digital serial interfaces provide the input to the DAC through a digital multiplexer. These interfaces
support several serial protocols including I²S, left-justified, and right-justified formats. The data format is
16-bit or 18-bit precision, with MSB first. There is also a DSP-compatible mode available.
All single-ended analog inputs can be passed through to the main output of the device by means of an analog
multiplexer. The differential TV baseband audio input (TV BASEBAND P, TV BASEBAND M) feeds a
monaural decoder which then feeds the same multiplexer.
2.1.1 Serial PCM Data Ports
The device includes two serial ports used to transfer digital audio data from an external digital source to the
DAC: The AUX serial port (ASDATA, ABCLK, and ALRCLK) can be configured to operate in either master
or slave mode. The main serial PCM port (SDATA, BCLK, and LRCLK) always operates in the slave mode.
Note, that the only exclusion is that the AUX port does not support the DSP mode when configured as
master.
Configuration of these serial ports is accomplished by means of the SPI-compatible control serial interface
port. Specifically, the protocol (Philips I²S protocol, left-justified, right-justified, or DSP mode), and data
format (16-bit or 18-bit) are selected by programming control register 00h. The multiplexer selection is
programmed with control register 01h which will also enable or disable these serial data ports.
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