TLC320AD80 Datasheet, PDF (20/37 Pages) Texas Instruments – Audio Processor Subsystem

The time-out feature of 4096 LRCLK periods can be eliminated by setting D7 of control register 04h, in which
case the data values must have a zero crossing for the next gain setting to be sent to the amplifier. This
feature is useful in applications where severe data latency is either expected or needed and an audio pop
is to be avoided. Many other multimedia applications such as acoustic echo cancellation will benefit from
this feature.
The 70th volume control setting corresponds to audio mute. Mute provides greater than 80 dB of attenuation
from a full-scale audio output.
It is possible for an audible click or pop to occur immediately after a zero crossing unmute. If an audio
amplifier needs to slew rate limit immediately after being unmuted to catch up with a rapidly changing audio
input, then that amplifier may subsequently overshoot causing an audible click or pop. By utilizing the
programmable volume control feature of the TLC320AD80, a soft mute function can be implemented in
software that eliminates this potential cause of audible noise. A soft mute would provide a gradual
attenuation change over an appropriate time interval when entering a muted condition rather than an
allowing an abrupt change to occur. The original volume control setting would be gradually restored upon
leaving a muted condition.
2.4 Sigma-Delta DAC
The sigma-delta DAC contains an interpolation filter and single bit modulator with 64 times oversampling.
The switched-capacitor and continuous time analog filter which follows, provides the smoothed analog
signal output.
2.4.1 Interpolator / Modulator
The interpolation filter receives 16-bit or 18-bit data at the sample rate and interpolates new values at a rate
of 64-times the sample rate. These values are provided to the sigma-delta modulator for noise shaping. The
output of the digital modulator is a one bit data stream which is sent to a switched capacitor filter.
2.4.2 Continuous Time and Switched Capacitor Filters
The switched capacitor filter performs the low-pass filter function. The filter characteristics are stated in the
specification section. The corner frequency of this filter is directly proportional to the selected sample rate.
The continuous time filter is used to reduce the switching frequency energy of the switched capacitor filter,
and any remaining high frequency energy. This switched-capacitor filter also provides the selectable 50/15
µs de-emphasis under control of register 02h.
2.5 Serial Control Port
The SPI-compatible serial port controls all the programmable states of the TLC320AD80. The 4-wire SPI
compatible interface is composed of a serial clock (SCLK), an active low chip select (CS), a command data
input (CDIN), and a command data output (CDOUT). There are five 8-bit control registers within the
TLC320AD80.
2.5.1 Serial Control Port Description
The serial control port is activated when the active low CS signal is asserted. The CS input must be asserted
low prior to a data transfer and must remain low for the duration of the transfer as shown in Figure 2–5.
The serial command data input (CDIN) is sampled with the rising edge of SCLK. The CDIN data is MSB first
and unsigned.
While the CS input is low, the SCLK input must idle high when there is no valid data to be transferred. The
first byte of CDIN data after CS activation is the serial control command. The serial control command
includes a 4-bit control register address [D(3–0)] and a control port direction bit (D7). The second byte of
data is the register data.
2–9