TLC320AD80 Datasheet, PDF (11/37 Pages) Texas Instruments – Audio Processor Subsystem

1.6 Terminal Functions (Continued)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
EXT OUTL
29
O Left channel fixed line level analog audio output. The EXT OUTL output
driver provides line level signals (1 Vrms max) for line output. The EXT OUTL
output is capable of driving a 10-kΩ load.
EXT OUTR
30
O Right channel fixed line level analog audio output. The EXT OUTR output
driver provides line level signals (1 Vrms max) for line output. The EXT OUTR
output is capable of driving a 10-kΩ load.
LRCLK
10
I Left/right channel indicator. LRCLK signifies whether the serial PCM data
(SDATA) is associated with the left channel DAC or the right channel DAC.
MCLK 1
4
I Master clock, sigma-delta DAC oversampling clock input. The
TLC320AD80 defaults to MCLK 1. The TLC320AD80 can run off of MCLK
1 or MCLK 2.
MCLK 2
3
I Auxiliary master clock, DAC oversampling clock input. The TLC320AD80
can run off of either MCLK 1 or MCLK 2.
MUX IN1
41
I Wideband multiplexer input 1
MUX IN2
42
I Wideband multiplexer input 2
MUX OUT
43
O Wideband multiplexer output. The multiplexer can output one of two inputs
(MUX IN1, MUX IN2) or perform an audio mute. The MUX OUT output is
capable of driving a 600-Ω load.
NTSCAUDIO L
19
I Left channel NTSC analog audio input
NTSCAUDIO R
20
I Right channel NTSC analog audio input
REF
47
I Voltage reference. The REF voltage provides a common mode reference of
2.25 V for all audio output drivers. The REF voltage can also be used as an
external common mode reference with the restriction that only a
high-impedance dc load should be applied. REF should be bypassed with
a 0.1 µF capacitor.
REFF
48
I Voltage reference filter. REFF is provided for low-pass filtering of the internal
voltage reference (3.2 V) for the sigma-delta DAC. REFF should be
bypassed with 10 µF and 0.1 µF capacitors. This voltage node should be
loaded only with a high-impedance dc load.
RESET
56
I Power down/reset. When RESET is held low, the TLC320AD80 is placed in
a power-down state. The TLC320AD80 is reset on the rising edge of RESET.
SCLK
60
I SPI bus serial clock input. Control input data (CDIN) must be valid on the
rising edge of SCLK. SCLK may be continuous or gated.
SDATA
8
I Serial PCM data input port. SDATA can be configured as 16 or 18 bits with
the MSB first, 2s complement format.
SUB
25
I Substrate ground connected to AGND plane.
TV BASEBAND P
53
I TV aural baseband multiplex noninverting input
TV BASEBAND M
54
I TV aural baseband multiplex inverting input
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