TLC320AD80 Datasheet, PDF (18/37 Pages) Texas Instruments – Audio Processor Subsystem

enough time for the voltage across the capacitors connecting the external stereo output to the external
stereo input to reach a steady state condition.
A similar approach is required to prevent audible clicks on the output of the wideband multiplexer. Prior to
each multiplexer input selection change, the multiplexer output should be muted by clearing bit D5 to 0 of
control register 02h. The output signal follows the currently selected multiplexer input until the next zero
crossing occurs which activates the mute. After a recommended time delay of 4096 LRCLK cycles, the
multiplexer input selection can be changed by writing to bit D2 of control register 01h. The multiplexer output
can then be unmuted by setting bit D5 to 1 of control register 02h. The output signal remains muted until
the next zero crossing occurs and then follows the newly selected multiplexer input.
2.1.4 Audio Input Port Mute and Capacitor Precharge Mode
The sigma-delta DAC and the monaural decoder may introduce offset errors that could cause audible clicks
or pops to occur during volume control changes. To prevent this audible noise, the external audio output
(EXT OUTL, EXT OUTR) should be connected to the external audio inputs (EXT INL, EXT INR) through
ac coupling capacitors to remove this offset error.
During source selection changes, sufficient time needs to be provided to allow the voltage across these
external capacitors to reach a steady state condition before returning the audio to an unmuted condition.
In order to minimize this required settling time, the input resistance of the external audio inputs can be reduce
by a factor of 10 by selecting the capacitor precharge mode. The input resistance of this port normally varies
as a function of the volume control setting. The input resistance is lowest (≥ 20 kΩ) when the volume control
is at its maximum setting of 6 dB. When the capacitor precharge mode is selected by setiing control register
01h to 1, the input resistance is reduced to approximately 2 kΩ.
The audio input port mute should be enabled when using the capacitor precharge mode by clearing bit D0
of control register 01h to 0. When the audio input port mute is enabled, the serial PCM audio data is disabled
(forced to 0) at the input to the sigma-delta DAC, the differential input to the monaural decoder is shorted,
and the remaining analog audio inputs are muted. This removes the signal content but not the offset error
of a particular audio channel which is necessary in the capacitor precharge mode since the time constant
may be insufficient to find the long term average of the selected audio signal.
The audio input port mute feature may also be used in conjunction with the volume control mute to provide
increased audio mute attenuation for the serial PCM audio inputs. This improved mute attenuation occurs
following 30 LRCLK cycles when the 0 input data propagates to the output of the sigma-delta DAC. The
serial PCM audio data is enabled and disabled at the beginning of an audio sample period (rising edge of
LRCLK) for an audio input port mute or unmute operation. The serial PCM data must be re-enabled prior
to requesting an unmuted volume control setting to provide the audio signal necessary to perform a zero
crossing unmute at the volume control stage.
2.2 Analog Audio Outputs
The TLC320AD80 analog outputs consist of two stereo outputs and two mono outputs. All are single-ended
analog outputs.
2.2.1 Variable Stereo Audio Outputs
The variable stereo audio output (AUDIO LEFT, AUDIO RIGHT) provides the output of the volume and
balance functional block. This output is intended as the final output of the TLC320AD80. In addition, one
of the mono outputs (AUDIO MONO) is derived from this stereo audio pair. The AUDIO MONO output is
the summation of the AUDIO LEFT and AUDIO RIGHT channels divided by 2.
The variable stereo audio output (AUDIO LEFT, AUDIO RIGHT) provides the selected audio input after
application of the volume control. The full-scale analog output of each channel is typically 2.8 V
peak-to-peak. These analog outputs can drive load impedances as low as 600 Ω and are short circuit
protected to 10 mA.
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