TLC320AD80 Datasheet, PDF (10/37 Pages) Texas Instruments – Audio Processor Subsystem

1.6 Terminal Functions
TERMINAL
I/O
NAME
NO.
AGND1
18
I
AGND2
45
I
AGND3
52
I
AUDIO LEFT
35
O
AUDIO MONO
39
O
AUDIO RIGHT
38
O
AUX AUDIO1L
AUX AUDIO1R
AUX AUDIO2M
ABCLK
ALRCLK
ASDATA
AVDD1
AVDD2
AVDD3
BCLK
BGFLTR
21
I
23
I
24
I
12
I/O
13
I/O
11
I
14
I
44
I
50
I
9
I
46
I
CDIN
61
I
CDOUT
CS
DGND1
DGND2
DVDD1
DVDD2
EXT INL
EXT INR
62
O
59
I
6
I
58
I
5
I
57
I
26
I
27
I
DESCRIPTION
Analog ground for sigma-delta DAC
Analog ground for analog audio output drivers
Analog ground for bandgap reference
Left channel line-level analog audio output. The AUDIO LEFT output driver
provides line level signals (1 Vrms max) for line output. The AUDIO LEFT
output is capable of driving a 600-Ω load.
Monaural variable line-level analog audio output. The AUDIO MONO output
signal is the sum of the AUDIO RIGHT and AUDIO LEFT outputs divided by
2. The output is capable of driving a 10-kΩ load.
Right channel variable line-level analog audio output. The AUDIO RIGHT
output driver provides line level signals (1 Vrms max) for line output. The
AUDIO RIGHT output is capable of driving a 600-Ω load.
Left channel auxiliary analog audio input 1
Right channel auxiliary analog audio input 1
Mono channel auxiliary analog audio input 2
Auxiliary serial bit clock input. The ABCLK bit clock signal clocks the serial
PCM data (ASDATA) into the TLC320AD80.
Auxiliary left/right channel indicator. ALRCLK signifies whether the serial
PCM data is associated with the left channel DAC or the right channel DAC.
Auxiliary serial PCM data input port. ASDATA can be configured as 16 or 18
bits with the most significant bit (MSB) first, 2’s complement format.
Analog 5-V power supply for the sigma-delta DAC
Analog 5-V power supply for the analog audio output drivers
Analog 5-V power supply for the bandgap reference
Serial bit clock input. BCLK clocks the serial PCM data (SDATA) into the
device.
Bandgap reference filter. BGFLTR provides for noise filtering of the internal
bandgap reference (2.25 V). BGFLTR requires a 0.1 µF capacitor to analog
ground. This voltage node should be loaded only with a high-impedance dc
load.
SPI bus serial control data input. Data is transferred MSB first. CDIN
specifies the channel specific attenuation and mute, serial PCM data format
and rates, de-emphasis mode, audio input port selection, and stereo or
monaural analog inputs.
SPI bus serial control data output port
SPI bus chip select input (active low)
Digital ground for the sigma-delta DAC
Digital ground for the serial interface
Digital 5-V power supply for the sigma-delta DAC
Digital 5-V power supply for the serial interface
Left channel external analog audio input
Right channel external analog audio input
1–5