AM3874_16 Datasheet, PDF (32/358 Pages) Texas Instruments – Sitara ARM Processors

AM3874, AM3871
SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016
www.ti.com
SIGNAL
NAME
GPMC_D[10]/
BTMODE[10]
GPMC_D[9]/
BTMODE[9]
GPMC_D[8]/
BTMODE[8]
GPMC_D[7]/
BTMODE[7]
GPMC_D[6]/
BTMODE[6]
GPMC_D[5]/
BTMODE[5]
GPMC_D[4]/
BTMODE[4]
GPMC_D[3]/
BTMODE[3]
GPMC_D[2]/
BTMODE[2]
GPMC_D[1]/
BTMODE[1]
GPMC_D[0]/
BTMODE[0]
Table 4-1. Boot Configuration Terminal Functions (continued)
TYPE ⁽¹⁾
NO.
OTHER ^{(2) (3)}
Y26
I
DIS
DVDD_GPMC
MUXED
DESCRIPTION
GPMC
PINCNTL99
DSIS: PIN
XIP (NOR) on GPMC Configuration. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, when the XIP (MUX0), XIP (MUX1),
XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode
is selected (see Table 5-1), BTMODE[10] is sampled to
select between GPMC pin muxing options A or B shown
in Table 5-2, XIP (on GPMC) Boot Options [Muxed or
Non-Muxed].
• 0 = GPMC Option A
• 1 = GPMC Option B
After reset, this pin functions as GPMC multiplexed
data/address pin 10 (GPMC_D[10]).
AB28
I
Y27
I
V25
I
U25
I
AA28
I
V26
I
W27
I
V27
I
Y28
I
U26
I
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
DIS
DVDD_GPMC
GPMC
PINCNTL98
DSIS: PIN
GPMC
PINCNTL97
DSIS: PIN
GPMC
PINCNTL96
DSIS: PIN
GPMC
PINCNTL95
DSIS: PIN
GPMC
PINCNTL94
DSIS: PIN
GPMC
PINCNTL93
DSIS: PIN
GPMC
PINCNTL92
DSIS: PIN
GPMC
PINCNTL91
DSIS: PIN
GPMC
PINCNTL90
DSIS: PIN
GPMC
PINCNTL89
DSIS: PIN
Ethernet PHY Configuration. These pins are multiplexed
between ARM Cortex-A8 boot mode and General-
Purpose Memory Controller (GPMC) peripheral functions.
At reset, when EMAC bootmode is selected (see Table 5-
1), BTMODE[9:8] pins are sampled to determine the
function of the Ethernet PHY Mode selection.
• 00 = MII (GMII)
• 01 = RMII
• 10 = RGMII
• 11 = Reserved
For more detailed information on the EMAC PHY boot
modes and the EMAC pin functions selected, see
Section 5.2.6, Ethernet PHY Mode Selection.
After reset, these pins function as GPMC multiplexed
data/address pins 9 and 8 (GPMC_D[9] and
GPMC_D[8]).
Reserved Boot Pins. These pins are multiplexed between
ARM Cortex-A8 boot mode and General-Purpose
Memory Controller (GPMC) peripheral functions.
For proper device operation at reset, these pins should
be externally pulled low.
After reset, these pins function as GPMC multiplexed
data/address pins 10 through 5 (GPMC_D[7:5]).
ARM Cortex-A8 Boot Mode Configuration Bits. These
pins are multiplexed between ARM Cortex-A8 boot mode
and the General-Purpose Memory Controller (GPMC)
peripheral functions.
At reset, the boot mode inputs BTMODE[4:0] are
sampled to determine the ARM boot configuration. For
more details on the types of boot modes supported, see
Section 5.2, Boot Modes, of this document, along with
the AM387x ROM Code Memory and Peripheral Booting
chapter of the AM387x Sitara™ ARM Processors
Technical Reference Manual (Literature Number:
SPRUGZ7).
After reset, these pins function as GPMC multiplexed
data/address pins 4 through 0 (GPMC_D[4:0]).
32
Device Pins
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