AM3874_16 Datasheet, PDF (228/358 Pages) Texas Instruments – Sitara ARM Processors

AM3874, AM3871
SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016
9.6.2.2 EMAC RMII Electrical Data/Timing
Table 9-20. Timing Requirements for EMAC[x]_RMREFCLK - RMII Operation
(see Figure 9-13)
OPP100/120/166
NO.
MIN
MAX
1
t_c(RMREFCLK)
2
t_w(RMREFCLKH)
3
t_w(RMREFCLKL)
4
t_t(RMREFCLK)
Cycle time, EMAC[x]_RMREFCLK
Pulse duration, EMAC[x]_RMREFCLK high
Pulse duration, EMAC[x]_RMREFCLK low
Transition time, EMAC[x]_RMREFCLK
19.999
7
7
20.001
13
13
3
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UNIT
ns
ns
ns
ns
1
2
4
RMREFCLK
(Input)
3
4
Figure 9-13. RMREFCLK Timing RMII Operation
Table 9-21. Timing Requirements for EMAC RMII Receive
(see Figure 9-13)
OPP100/120/166
NO.
MIN
MAX
t_{su(RMRXD-RMREFCLK)}
1
t_{su(RMCRSDV-RMREFCLK)}
Setup time, receive selected signals valid before
EMAC[x]_RMREFCLK
4
t_{su(RMRXER-RMREFCLK)}
t_{h(RMREFCLK-RMRXD)}
2
t_{h(RMREFCLK-RMCRSDV)}
Hold time, receive selected signals valid after
EMAC[x]_RMREFCLK
2
t_{h(RMREFCLK-RMRXER)}
UNIT
ns
ns
1
2
RMREFCLK
RMRXD1−RMRXD0,
RMCRSDV, RMRXER (inputs)
Figure 9-14. EMAC Receive Interface Timing RMII Operation
Table 9-22. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit
10/100 Mbits/s
(see Figure 9-15)
NO.
PARAMETER
OPP100/120/166
UNIT
MIN
MAX
1 t_{d(RMREFCLK-RMTXD)}
Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXD[x]
valid
2.5
13 ns
2 t_{dd(RMREFCLK-RMTXEN)}
Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXEN
valid
2.5
13
228 Peripheral Information and Timings
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