AM3874_16 Datasheet, PDF (19/358 Pages) Texas Instruments – Sitara ARM Processors

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AM3874, AM3871
SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016
Cortex-A8 and L3 Masters
START ADDRESS
(HEX)
END ADDRESS
(HEX)
0x4819_D000
0x4819_DFFF
0x4819_E000
0x4819_EFFF
0x4819_F000
0x4819_FFFF
0x481A_0000
0x481A_0FFF
0x481A_1000
0x481A_1FFF
0x481A_2000
0x481A_2FFF
0x481A_3000
0x481A_3FFF
0x481A_4000
0x481A_4FFF
0x481A_5000
0x481A_5FFF
0x481A_6000
0x481A_6FFF
0x481A_7000
0x481A_7FFF
0x481A_8000
0x481A_8FFF
0x481A_9000
0x481A_9FFF
0x481A_A000
0x481A_AFFF
0x481A_B000
0x481A_BFFF
0x481A_C000
0x481A_CFFF
0x481A_D000
0x481A_DFFF
0x481A_E000
0x481A_EFFF
0x481A_F000
0x481A_FFFF
0x481B_0000
0x481B_FFFF
0x481C_0000
0x481C_0FFF
0x481C_1000
0x481C_1FFF
0x481C_2000
0x481C_2FFF
0x481C_3000
0x481C_3FFF
0x481C_4000
0x481C_4FFF
0x481C_5000
0x481C_5FFF
0x481C_6000
0x481C_6FFF
0x481C_7000
0x481C_7FFF
0x481C_8000
0x481C_8FFF
0x481C_9000
0x481C_9FFF
0x481C_A000
0x481C_BFFF
0x481C_C000
0x481C_DFFF
0x481C_E000
0x481C_FFFF
0x481D_0000
0x481D_1FFF
0x481D_2000
0x481D_3FFF
0x481D_4000
0x481D_5FFF
0x481D_6000
0x481D_6FFF
0x481D_7000
0x481D_7FFF
0x481D_8000
0x481E_7FFF
0x481E_8000
0x481E_8FFF
0x481E_9000
0x481F_FFFF
0x4820_0000
0x4820_0FFF
0x4820_1000
0x4823_FFFF
0x4824_0000
0x4824_0FFF
0x4824_1000
0x4827_FFFF
SIZE
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
64KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
4KB
4KB
64KB
4KB
52KB
4KB
252KB
4KB
252KB
DEVICE NAME
I2C2 Support Registers
I2C3 Peripheral Registers
I2C3 Support Registers
SPI1 Peripheral Registers
SPI1 Support Registers
SPI2 Peripheral Registers
SPI2 Support Registers
SPI3 Peripheral Registers
SPI3 Support Registers
UART3 Peripheral Registers
UART3 Support Registers
UART4 Peripheral Registers
UART4 Support Registers
UART5 Peripheral Registers
UART5 Support Registers
GPIO2 Peripheral Registers
GPIO2 Support Registers
GPIO3 Peripheral Registers
GPIO3 Support Registers
Reserved
Reserved
TIMER8 Peripheral Registers
TIMER8 Support Registers
SYNCTIMER32K Peripheral Registers
SYNCTIMER32K Support Registers
PLLSS Peripheral Registers
PLLSS
WDT0 Peripheral Registers
WDT0 Support Registers
Reserved
Reserved
DCAN0 Peripheral Registers
DCAN0 Support Registers
DCAN1 Peripheral Registers
DCAN1 Support Registers
Reserved
Reserved
Reserved
MMC/SD/SDIO1 Peripheral Registers
MMC/SD/SDIO1 Support Registers
Reserved
Interrupt controller⁽¹⁾
Reserved ⁽¹⁾
MPUSS config register⁽¹⁾
Reserved ⁽¹⁾
(1) These regions decoded internally by the Cortex-A8 Subsystem and are not physically part of the L4 Slow. They are included here only
for reference when considering the Cortex-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.
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