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AM3874_16 Datasheet, PDF (230/358 Pages) Texas Instruments – Sitara ARM Processors
◁
AM3874, AM3871
SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016
www.ti.com
Table 9-24. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps(1)
(see Figure 9-16)
OPP100/120/166
NO.
UNIT
MIN
MAX
5
tsu(RGRXD-
RGRXCH)
Setup time, receive selected signals valid before EMAC[x]_RGRXC (at device)
high/low
1.0
ns
6
th(RGRXCH-
RGRXD)
Hold time, receive selected signals valid after EMAC[x]_RGRXC (at device)
high/low
1.0
ns
(1) For RGMII, receive selected signals include: EMAC[x]_RGRXD[3:0] and EMAC[x]_RGRXCTL.
EMAC[x]_RGRXC
(at device)(A)
EMAC[x]_RGRXD[3:0](B)
1
2
3
4
4
5
1st Half-byte
2nd Half-byte
6
RGRXD[3:0] RGRXD[7:4]
EMAC[x]_RGRXCTL(B)
RXDV
RXERR
A. EMAC[x]_RGRXC must be externally delayed relative to the data and control pins. The internal delay can be enabled
or disabled via the EMAC RGMIIx_ID_MODE register.
B. Data and control information is received using both edges of the clocks. EMAC[x]_RGRXD[3:0] carries data bits 3-0
on the rising edge of EMAC[x]_RGRXC and data bits 7-4 on the falling edge of EMAC[x]_RGRXC. Similarly,
EMAC[x]_RGRXCTL carries RXDV on rising edge of EMAC[x]_RGRXC and RXERR on falling edge of
EMAC[x]_RGRXC.
Figure 9-16. EMAC Receive Interface Timing [RGMII Operation]
Table 9-25. Switching Characteristics Over Recommended Operating Conditions for RGTXC - RGMII
Operation for 10/100/1000 Mbit/s
(see Figure 9-17)
OPP100/120/166
NO.
UNIT
MIN
MAX
10 Mbps
360
440
1
tc(RGTXC)
Cycle time, EMAC[x]_RGTXC
100 Mbps
1000 Mbps
36
44 ns
7.2
8.8
2
tw(RGTXCH) Pulse duration, EMAC[x]_RGTXC high
3
tw(RGTXCL) Pulse duration, EMAC[x]_RGTXC low
10 Mbps
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
10 Mbps
0.40*tc(RGTXC) 0.60*tc(RGTXC)
0.40*tc(RGTXC) 0.60*tc(RGTXC)
ns
0.45*tc(RGTXC) 0.55*tc(RGTXC)
0.40*tc(RGTXC) 0.60*tc(RGTXC)
0.40*tc(RGTXC) 0.60*tc(RGTXC)
ns
0.45*tc(RGTXC) 0.55*tc(RGTXC)
0.75
4
tt(RGTXC)
Transition time, EMAC[x]_RGTXC
100 Mbps
1000 Mbps
0.75 ns
0.75
230 Peripheral Information and Timings
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