AM3874_16 Datasheet, PDF (314/358 Pages) Texas Instruments – Sitara ARM Processors

AM3874, AM3871
SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016
www.ti.com
HEX ADDRESS
0x4700 0118
0x4700 011C
0x4700 0120
0x4700 0124
0x4700 0128
0x4700 012C
0x4700 0130
0x4700 0134
0x4700 0138
0x4700 013C
0x4700 0140
0x4700 0144
0x4700 0148
0x4700 014C
0x4700 0150
0x4700 0154
0x4700 0158
0x4700 015C
0x4700 0160
0x4700 0164
0x4700 0168
0x4700 016C
0x4700 0170
0x4700 0174
0x4700 0178
0x4700 017C
0x4700 0180
0x4700 0184
0x4700 0188
0x4700 018C
0x4700 0190
0x4700 0194
0x4700 01A0
0x4700 01A4
0x4700 01A8
0x4700 01AC
0x4700 01B0
0x4700 01B4
0x4700 01B8
0x4700 01C0
Table 9-80. McBSP Registers⁽¹⁾ (continued)
ACRONYM
RCR2_REG
RCR1_REG
XCR2_REG
XCR1_REG
SRGR2_REG
SRGR1_REG
MCR2_REG
MCR1_REG
RCERA_REG
RCERB_REG
XCERA_REG
XCERB_REG
PCR_REG
RCERC_REG
RCERD_REG
XCERC_REG
XCERD_REG
RCERE_REG
RCERF_REG
XCERE_REG
XCERF_REG
RCERG_REG
RCERH_REG
XCERG_REG
XCERH_REG
REV_REG
RINTCLR_REG
XINTCLR_REG
ROVFLCLR_REG
SYSCONFIG_REG
THRSH2_REG
THRSH1_REG
IRQSTATATUS
IRQENABLE
WAKEUPEN
XCCR_REG
RCCR_REG
XBUFFSTAT_REG
RBUFFSTAT_REG
STATUS_REG
REGISTER NAME
McBSP receive control 2
McBSP receive control 1
McBSP transmit control 2
McBSP transmit control 1
McBSP sample rate generator 2
McBSP sample rate generator 1
McBSP multichannel 2
McBSP multichannel 1
McBSP receive channel enable partition A
McBSP receive channel enable partition B
McBSP transmit channel enable partition A
McBSP transmit channel enable partition B
McBSP pin control
McBSP receive channel enable partition C
McBSP receive channel enable partition D
McBSP transmit channel enable partition C
McBSP transmit channel enable partition D
McBSP receive channel enable partition E
McBSP receive channel enable partition F
McBSP transmit channel enable partition E
McBSP transmit channel enable partition F
McBSP receive channel enable partition G
McBSP receive channel enable partition H
McBSP transmit channel enable partition G
McBSP transmit channel enable partition H
McBSP revision number
McBSP receive interrupt clear
McBSP transmit interrupt clear
McBSP receive overflow interrupt clear
McBSP system configuration
McBSP transmit buffer threshold (DMA or IRQ trigger)
McBSP receive buffer threshold (DMA or IRQ trigger)
McBSP interrupt status (OCP compliant IRQ line)
McBSP interrupt enable (OCP compliant IRQ line)
McBSP wakeup enable
McBSP transmit configuration control
McBSP receive configuration control
McBSP transmit buffer status
McBSP receive buffer status
McBSP status
314 Peripheral Information and Timings
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