AM3874_16 Datasheet, PDF (223/358 Pages) Texas Instruments – Sitara ARM Processors

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AM3874, AM3871
SPRS695D – SEPTEMBER 2011 – REVISED JANUARY 2016
Table 9-14. Ethernet MAC Switch Registers (continued)
ARM/L3 MASTERS
EMAC HEX
ADDRESS RANGE
0x4A10 0464
0x4A10 0468
0x4A10 046C
0x4A10 0470
0x4A10 0474
0x4A10 0478
0x4A10 047C
0x4A10 0480
0x4A10 0484
0x4A10 0488
0x4A10 048C
0x4A10 0490 - 0x4A10 04FC
0x4A10 0500
0x4A10 0504
0x4A10 0508
0x4A10 050C
0x4A10 0510
0x4A10 0514
0x4A10 0518 - 0x4A10 051C
0x4A10 0520
0x4A10 0524
0x4A10 0528
0x4A10 052C
0x4A10 0530
0x4A10 0534
0x4A10 0538
0x4A10 053C - 0x4A10 05FC
0x4A10 0600
0x4A10 0604
0x4A10 0608
0x4A10 060C
0x4A10 0610
0x4A10 0614
0x4A10 0618
0x4A10 061C
0x4A10 0620
0x4A10 0624 - 0x4A10 0630
0x4A10 0634
0x4A10 0638
0x4A10 063C
0x4A10 0640
0x4A10 0644
0x4A10 0648
0x4A10 064C
0x4A10 0650
ACRONYM
REGISTER NAME
TXOCTETS
CPSW_STATS TxOctets
64OCTETFRAMES
CPSW_STATS 64octetFrames
65T127OCTETFRAMES CPSW_STATS 65-127octetFrames
128T255OCTETFRAMES CPSW_STATS 128-255octetFrames
256T511OCTETFRAMES CPSW_STATS 256-511octetFrames
512T1023OCTETFRAMES CPSW_STATS 512-1023octetFrames
1024TUPOCTETFRAMES CPSW_STATS 1023-1518octetFrames
NETOCTETS
CPSW_STATS NetOctets
RXSOFOVERRUNS CPSW_STATS Receive FIFO or DMA Start of Frame Overruns
RXMOFOVERRUNS CPSW_STATS Receive FIFO or DMA Mid of Frame Overruns
RXDMAOVERRUNS
CPSW_STATS Receive DMA Start of Frame and Middle of Frame
Overruns
–
Reserved
CPTS_IDVER
Identification and Version Register
CPTS_CONTROL
Time Sync Control Register
CPTS_RFTCLK_SEL Reference Clock Select Register
CPTS_TS_PUSH
Time Stamp Event Push Register
CPTS_TS_LOAD_VAL Time Stamp Load Value Register
CPTSTS_LOAD_EN Time Stamp Load Enable Register
–
Reserved
CPTS_INTSTAT_RAW Time Sync Interrupt Status Raw Register
CPTS_INTSTAT_MASKED Time Sync Interrupt Status Masked Register
CPTS_INT_ENABLE Time Sync Interrupt Enable Register
–
Reserved
CPTS_EVENT_POP Event Interrupt Pop Register
CPTS_EVENT_LOW Lower 32-Bits of the Event Value
CPTS_EVENT_HIGH Upper 32-Bits of the Event Value
–
Reserved
ALE_IDVER
Address Lookup Engine ID/Version Register
–
Reserved
ALE_CONTROL
Address Lookup Engine Control Register
–
Reserved
ALE_PRESCALE
Address Lookup Engine Prescale Register
–
Reserved
ALE_UNKNOWN_VLAN Address Lookup Engine Unknown VLAN Register
–
Reserved
ALE_TBLCTL
Address Lookup Engine Table Control
–
Reserved
ALE_TBLW2
Address Lookup Engine Table Word 2 Register
ALE_TBLW1
Address Lookup Engine Table Word 1 Register
ALE_TBLW0
Address Lookup Engine Table Word 0 Register
ALE_PORTCTL0
Address Lookup Engine Port 0 Control Register
ALE_PORTCTL1
Address Lookup Engine Port 1 Control Register
ALE_PORTCTL2
Address Lookup Engine Port 2 Control Register
–
Reserved
–
Reserved
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Peripheral Information and Timings 223