LM3S1969 Datasheet, PDF (290/677 Pages) Texas Instruments – Stellaris® LM3S1969 Microcontroller

OBSOLETE: TI has discontinued production of this device.
General-Purpose Input/Outputs (GPIOs)
(see page 303) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see
page 313) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see
page 314) have been set to 1.
8.2.5
Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the V_OL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package with the total number of high-current GPIO
outputs not exceeding four for the entire package.
8.2.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
8.3 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven
(tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-4 on page 290
shows all possible configurations of the GPIO pads and the control register settings required to
achieve them. Table 8-5 on page 291 shows how a rising edge interrupt would be configured for pin
2 of a GPIO port.
Table 8-4. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I²C)
Digital Input (Timer
1
X
0
1
CCP)
Digital Input (QEI)
1
X
0
1
Digital Output (PWM)
1
X
0
1
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
PUR
?
?
X
X
?
?
?
?
?
PDR
?
?
X
X
?
?
?
?
?
DR2R
X
?
?
?
X
X
?
?
?
DR4R
X
?
?
?
X
X
?
?
?
DR8R
X
?
?
?
X
X
?
?
?
SLR
X
?
?
?
X
X
?
?
?
290
July 24, 2012
Texas Instruments-Production Data