LM3S1969 Datasheet, PDF (287/677 Pages) Texas Instruments – Stellaris® LM3S1969 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S1969 Microcontroller
8.2 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 287). The LM3S1969 microcontroller contains eight ports and thus eight of these physical
GPIO blocks.
Figure 8-1. GPIO Port Block Diagram
Commit
Control
GPIOLOCK
GPIOCR
Alternate Input
Alternate Output
Alternate Output Enable
Data
Control
GPIODATA
GPIODIR
Mode
Control
GPIOAFSEL
GPIO Input
GPIO Output
GPIO Output Enable
Pad Input
Pad Output
Pad Output Enable
Digital
I/O Pad
Package I/O Pin
Interrupt
Interrupt
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Pad
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
July 24, 2012
287
Texas Instruments-Production Data