LM3S1969 Datasheet, PDF (21/677 Pages) Texas Instruments – Stellaris® LM3S1969 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S1969 Microcontroller
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 436
UART Flag (UARTFR), offset 0x018 ................................................................................ 438
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 440
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 441
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 442
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 443
UART Control (UARTCTL), offset 0x030 ......................................................................... 445
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 447
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 449
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 451
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 452
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 453
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 455
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 456
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 457
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 458
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 459
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 460
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 461
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 462
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 463
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 464
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 465
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 466
Synchronous Serial Interface (SSI) ............................................................................................ 467
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 480
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 482
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 484
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 485
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 487
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 488
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 490
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 491
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 492
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 493
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 494
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 495
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 496
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 497
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 498
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 499
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 500
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 501
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 502
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 503
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 504
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 505
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 521
July 24, 2012
21
Texas Instruments-Production Data