LM3S1969 Datasheet, PDF (22/677 Pages) Texas Instruments – Stellaris® LM3S1969 Microcontroller

Table of Contents
OBSOLETE: TI has discontinued production of this device.
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 522
I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 526
I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 527
I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 528
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 529
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 530
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 531
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 532
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 534
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 535
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 537
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 538
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 539
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 540
I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 541
Analog Comparators ................................................................................................................... 542
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 547
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 548
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 549
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 550
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 551
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 551
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... 551
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 552
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 552
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 552
Pulse Width Modulator (PWM) .................................................................................................... 554
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 564
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 565
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 566
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 567
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 568
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 569
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 570
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 571
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 572
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 573
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 573
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 573
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 575
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 575
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 575
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 578
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 578
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 578
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 579
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 579
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July 24, 2012
Texas Instruments-Production Data