LM3S1969 Datasheet, PDF (11/677 Pages) Texas Instruments – Stellaris® LM3S1969 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S1969 Microcontroller
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 474
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 475
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 475
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 476
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 477
Figure 14-1. I²C Block Diagram ............................................................................................. 506
Figure 14-2. I²C Bus Configuration ........................................................................................ 507
Figure 14-3. START and STOP Conditions ............................................................................. 507
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 508
Figure 14-5. R/S Bit in First Byte ............................................................................................ 508
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 508
Figure 14-7. Master Single SEND .......................................................................................... 512
Figure 14-8. Master Single RECEIVE ..................................................................................... 513
Figure 14-9. Master Burst SEND ........................................................................................... 514
Figure 14-10. Master Burst RECEIVE ...................................................................................... 515
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 516
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 517
Figure 14-13. Slave Command Sequence ................................................................................ 518
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 543
Figure 15-2. Structure of Comparator Unit .............................................................................. 544
Figure 15-3. Comparator Internal Reference Structure ............................................................ 545
Figure 16-1. PWM Unit Diagram ............................................................................................ 555
Figure 16-2. PWM Module Block Diagram .............................................................................. 556
Figure 16-3. PWM Count-Down Mode .................................................................................... 557
Figure 16-4. PWM Count-Up/Down Mode .............................................................................. 558
Figure 16-5. PWM Generation Example In Count-Up/Down Mode ........................................... 558
Figure 16-6. PWM Dead-Band Generator ............................................................................... 559
Figure 17-1. QEI Block Diagram ............................................................................................ 594
Figure 17-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 595
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 611
Figure 21-1. Load Conditions ................................................................................................ 631
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 634
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 634
Figure 21-4. JTAG TRST Timing ............................................................................................ 634
Figure 21-5. External Reset Timing (RST) .............................................................................. 635
Figure 21-6. Power-On Reset Timing ..................................................................................... 635
Figure 21-7. Brown-Out Reset Timing .................................................................................... 636
Figure 21-8. Software Reset Timing ....................................................................................... 636
Figure 21-9. Watchdog Reset Timing ..................................................................................... 636
Figure 21-10. Hibernation Module Timing ................................................................................. 637
Figure 21-11. ADC Input Equivalency Diagram ......................................................................... 638
Figure 21-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 639
Figure 21-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 640
Figure 21-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 640
Figure 21-15. I²C Timing ......................................................................................................... 641
Figure D-1. Stellaris LM3S1969 100-Pin LQFP Package Dimensions ..................................... 672
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 674
July 24, 2012
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Texas Instruments-Production Data