LM3S1969 Datasheet, PDF (259/677 Pages) Texas Instruments – Stellaris® LM3S1969 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S1969 Microcontroller
7.2.2.3
7.3
7.3.1
Table 7-1. Flash Protection Policy Combinations (continued)
FMPPEn
1
0
1
FMPREn
0
1
1
Protection
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register. Details on programming these bits
are discussed in “Nonvolatile Register Programming” on page 260.
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 268) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 267).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 269).
Flash Memory Initialization and Configuration
Flash Programming
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD, and FMC.
During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAM and executed from there while the flash operation is in progress.
July 24, 2012
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