TLC5948A Datasheet, PDF (28/50 Pages) Texas Instruments – 16-Channel, 16-Bit, ES-PWM, Full Self-Diagnosis LED Driver

TLC5948A
SBVS192 – MARCH 2012
www.ti.com
257-Bit Common Shift Register
The 257-bit common shift register is used to shift data from the SIN pin into the TLC5948A. The data shifted into
the register are used for GS, DC, and global BC functions. The common shift register LSB is connected to SIN
and the MSB is connected to SOUT. On each SCLK rising edge, the data on SIN are shifted into the LSB and all
257 bits are shifted towards the MSB. The register MSB is always connected to SOUT. When the device is
powered up, the data in the 257-bit common shift register are random.
First and Second Grayscale (GS) Data Latch
The first and second GS data latches are each 256 bits long, and set the PWM timing for each constant-current
output. The on-time of all constant-current outputs is controlled by the data in the second GS data latch. A LAT
rising edge when the common shift register MSB is '0' shifts the least significant 256 bits of the common shift
register into the first GS latch. The GS data from the first latch are copied into the second latch either when the
65,536th GSCLK occurs with the auto display repeat mode enabled, or a LAT rising edge for a GS data write
occurs with the display timing reset mode enabled, or the BLANK bit in the first control data latch is set to '1'.
When the device is powered up, the data in the first and second latches are random. Therefore, GS data must
be written to the GS data latches before turning on the constant-current output. The first and second GS data
latch configurations are shown in Figure 31. The data bit assignment is shown in Table 7.
From Common Shift Register
First Grayscale (GS) Data Latch (256 Bits)
256 Bits
MSB
255
OUT15
Bit 15
240
OUT15
Bit 0
GS Data for OUT15
48
47
OUT3 OUT2
Bit 0 Bit 15
32
31
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
This latch pulse comes
from the LAT pin when
the MSB of the Common
Shift Register is ‘0’.
Second Grayscale (GS) Data Latch (256 Bits)
256 Bits
MSB
255
240
48
47
32
31
OUT15
Bit 15
OUT15
Bit 0
OUT3 OUT2
Bit 0 Bit 15
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
The 65,536th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to ‘1’.
256 Bits
To GS Timing Control Circuit
Figure 31. First and Second Grayscale Data Latch Configuration
BIT NUMBER
15-0
31-16
47-32
63-48
79-64
95-80
111-96
127-112
Table 7. Grayscale Data Latch Bit Description
BIT NAME
GSOUT0
GSOUT1
GSOUT2
GSOUT3
GSOUT4
GSOUT5
GSOUT6
GSOUT7
CONTROLLED
CHANNEL
Bits[15:0] for OUT0
Bits[15:0] for OUT1
Bits[15:0] for OUT2
Bits[15:0] for OUT3
Bits[15:0] for OUT4
Bits[15:0] for OUT5
Bits[15:0] for OUT6
Bits[15:0] for OUT7
BIT NUMBER
143-128
159-144
175-160
191-176
207-192
223-208
239-224
255-240
BIT NAME
GSOUT8
GSOUT9
GSOUT10
GSOUT11
GSOUT12
GSOUT13
GSOUT14
GSOUT15
CONTROLLED
CHANNEL
Bits[15:0] for OUT8
Bits[15:0] for OUT9
Bits[15:0] for OUT10
Bits[15:0] for OUT11
Bits[15:0] for OUT12
Bits[15:0] for OUT13
Bits[15:0] for OUT14
Bits[15:0] for OUT15
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