TLC5948A Datasheet, PDF(21/50 Page) Texas Instruments – 16-Channel, 16-Bit, ES-PWM, Full Self-Diagnosis LED Driver

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TLC5948A Datasheet, PDF (21/50 Pages) Texas Instruments – 16-Channel, 16-Bit, ES-PWM, Full Self-Diagnosis LED Driver

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TLC5948A

www.ti.com

SBVS192 â MARCH 2012

Table 5 summarizes the GS data values versus the output on-time duty cycle. When the device powers up, the

BLANK bit in the first control data latch is set to '1'. The 257-bit common shift register and the first and second

GS data latches contain random data. Therefore, GS data must be written to the GS latches before the BLANK

bit is set to '0'. All constant-current outputs are off when the BLANK bit is '1'.

GS DATA

DECIMAL

8191

8192

8193

16381

16382

16383

16384

16385

16386

16387

24575

24576

24577

32765

32766

32767

Table 5. Output Duty Cycle and On-Time versus GS Data

HEX

1FFF

2000

2001

3FFD

3FFE

3FFF

4000

4001

4002

4003

5FFF

6000

6001

7FFD

7FFE

7FFF

ON-TIME DUTY (%)

0.002

0.003

0.005

12.499

12.500

12.502

24.996

24.997

24.999

25.000

25.002

25.003

25.005

37.499

37.501

37.502

49.996

49.998

49.999

GS DATA

DECIMAL

32768

32769

32770

32771

40959

40960

40961

49149

49150

49151

49152

49153

49154

49155

57343

57344

57345

65533

65534

65535

HEX

8000

8001

8002

8003

9FFF

A000

A001

BFFD

BFFE

BFFF

C000

C001

C002

C003

DFFF

E000

E001

FFFD

FFFE

FFFF

ON-TIME DUTY (%)

50.001

50.002

50.004

50.005

62.499

62.501

62.502

74.997

74.998

75.000

75.001

75.003

75.004

75.006

87.500

87.501

87.503

99.997

99.998

100.000

Conventional PWM Control

In this PWM control, the GS clock is enabled when the BLANK bit is set to '0'. The first GS clock rising edge after

the BLANK bit is set to '0' increments the GS counter by one and switches on all outputs with a non-zero GS

value programmed into the second GS data latch. Each additional GS clock rising edge increases the

corresponding GS counter by one.

The GS counter keeps track of the number of clock pulses from the GS clock inputs. Each output stays on while

the counter is less than or equal to the programmed GS value. Each output turns off at the GS counter value

rising edge when the counter becomes greater than the output GS latch value. Figure 25 illustrates the

conventional PWM operation.

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