TLC5948A Datasheet, PDF (27/50 Pages) Texas Instruments – 16-Channel, 16-Bit, ES-PWM, Full Self-Diagnosis LED Driver

TLC5948A
www.ti.com
SBVS192 – MARCH 2012
REGISTER AND DATA LATCH CONFIGURATION
The TLC5948A has one common shift register and two pairs of data latches: the first and second grayscale (GS)
data latches and the first and second control data latches. The common shift register is 257 bits long and the GS
data latches are 256 bits long in total. The first control data latch is 137 bits long and the second latch is 119 bits
long. When the common shift register MSB is '0', the least significant 256 bits from the common shift register are
latched into the first GS data latch. When the MSB is '1', the data are latched into the first control data latch.
Figure 30 shows the common shift register and latch configurations.
Common Shift Register (257 Bits)
SOUT
MSB
Latch Common Common Common Common Common
Select Data Bit Data Bit Data Bit Data Bit Data Bit
Bit
255
254
253
252
251
256
255
254
253
252
251
LSB
Common Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit
5
4
3
2
1
0
5
4
3
2
1
0
SIN
SCLK
Lower 256 Bits
First Grayscale (GS) Data Latch (256 Bits)
256 Bits
MSB
255
240
48
47
32
31
OUT15
Bit 15
OUT15
Bit 0
OUT3 OUT2
Bit 0 Bit 15
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
This latch pulse comes
from the LAT pin when
the MSB of the Common
Shift Register is '0'.
Second Grayscale (GS) Data Latch (256 Bits)
256 Bits
MSB
255
240
48
47
32
31
OUT15
Bit 15
OUT15
Bit 0
OUT3 OUT2
Bit 0 Bit 15
OUT2 OUT1
Bit 0 Bit 15
16
15
OUT1 OUT0
Bit 0 Bit 15
LSB
0
OUT0
Bit 0
GS Data for OUT15
GS Data for OUT2
GS Data for OUT1
GS Data for OUT0
The 65,536th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to '1'.
256 Bits
To GS Timing Control Circuit
First Control Data Latch (137 Bits)
Lower 137 Bits of 256 Bits
MSB
136-119 118-112 111-105 104-98
FUNC
Bits
17-0
BC
Bits[6:0]
for OUTn
DC
Bits[6:0]
OUT15
DC
Bits[6:0]
OUT14
FC,
BC,
18 Bits 7 Bits
97-91
DC
Bits[6:0]
OUT13
90-84
DC
Bits[6:0]
OUT12
27-21
DC
Bits[6:0]
OUT3
DC, 112 Bits
20-14
DC
Bits[6:0]
OUT2
13-7
DC
Bits[6:0]
OUT1
LSB
6-0
DC
Bits[6:0]
OUT0
Second Control Data Latch (119 Bits)
119 Bits
18 Bits
MSB
118-112 111-105 104-98 97-91 90-84
LSB
27-21 20-14 13-7
6-0
BC
Bits[6:0]
for OUTn
DC
Bits[6:0]
OUT15
DC
Bits[6:0]
OUT14
DC
Bits[6:0]
OUT13
DC
Bits[6:0]
OUT12
DC
Bits[6:0]
OUT3
DC
Bits[6:0]
OUT2
DC
Bits[6:0]
OUT1
DC
Bits[6:0]
OUT0
BC,
7 Bits
DC, 112 Bits
7 Bits
112 Bits
This latch pulse
comes from the
LAT pin when the
MSB of the Common
Shift Register is ‘1’.
The 65,536th GSCLK is used
to latch the data when the
Auto Display Repeat is
enabled or when the BLANK bit
is set to '1'.
To
To
Function Global Brightness
Control Circuit Control Circuit
To
Dot Correction
Circuit
Figure 30. Common Shift Register and Control Data Latches Configuration
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): TLC5948A
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