TLC5948A Datasheet, PDF (13/50 Pages) Texas Instruments – 16-Channel, 16-Bit, ES-PWM, Full Self-Diagnosis LED Driver

TLC5948A
www.ti.com
PIN
NAME
NO.
GND
1
GSCLK
21
IREF
23
LAT
4
OUT0
5
OUT1
6
OUT2
7
OUT3
8
OUT4
9
OUT5
10
OUT6
11
OUT7
12
OUT8
13
OUT9
14
OUT10
15
OUT11
16
OUT12
17
OUT13
18
OUT14
19
OUT15
20
SCLK
3
SIN
2
SOUT
22
VCC
24
PIN DESCRIPTIONS
SBVS192 – MARCH 2012
I/O
DESCRIPTION
— Power ground
Grayscale (GS) pulse width modulation (PWM) reference clock control for OUTn.
I
When BLANK = 0, each GSCLK rising edge increments the GS counter for PWM control.
When BLANK = 0, all constant-current outputs (OUT0 to OUT15) are forced off, the GS counter is
reset to '0', and the GS PWM timing controller is initialized.
Reference current terminal.
I/O
A resistor connected between IREF to GND sets the maximum current for all constant-current outputs.
When IREF is shorted to GND with low resistance, all constant-current outputs are forced off and the
IREF short flag (ISF) bit in the status information data (SID) is set to '1'.
The LAT rising edge either latches the data from the 257-bit common shift register into the first GS
data latch when the common shift register MSB is '0' or it latches the data into the first control data
latch when the common shift register MSB is '1'.
I When the display timing reset bit (TMGRST) in the first control data latch is '1', the GS counter is
initialized at the LAT signal for GS data writes. At the same time, the data in the 257-bit common shift
register are copied to the first and second GS data latches simultaneously and the DC and BC data in
the first control data latch are copied to the second data latch.
O
O
O
O
O
O
O
O ^{Constant-current outputs.}
Multiple outputs can be configured in parallel to increase the constant-current capability.
O _{Different voltages can be applied to each output.}
O
O
O
O
O
O
O
Serial data shift clock.
I
Data present on SIN are shifted to the 257-bit common shift register LSB with the SCLK rising edge.
Data in the shift register are shifted towards the MSB at each SCLK rising edge.
The common shift register MSB appears on SOUT.
I 257-bit common shift register serial data input.
257-bit common shift register serial data output.
LED open detection (LOD), LED short detection (LSD), output leak detection (OLD), thermal error flag
O
(TEF), and the IREF pin short flag (ISF) bit can be read out with SOUT as SID after the LAT rising
edge.
SOUT is connected to the 257-bit common shift register MSB. Data are clocked out at the SCLK rising
edge.
— Power-supply voltage
Copyright © 2012, Texas Instruments Incorporated
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