TLC5948A Datasheet, PDF (25/50 Pages) Texas Instruments – 16-Channel, 16-Bit, ES-PWM, Full Self-Diagnosis LED Driver

TLC5948A
www.ti.com
SBVS192 – MARCH 2012
Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 27. This
function is switched on or off by the content of the DSPRPT bit in the first control data latch.
When the DSPRPT bit is '1', auto display repeat is enabled and the entire display period automatically repeats.
The entire display period only executes once after either the BLANK bit is set to '0', or after a LAT signal rising
edge for a GS data write is input when the display timing reset is enabled.
BLANK Bit
in First Control Data Latch
(Internal)
GSCLK
DSPRPT Bit
in First Control Data Latch
(Internal)
BLANK = 1 (Blank)
12345
BLANK = 0 (Not Blank)
65534 1
4
65535 2
5
65533 65536 3
65534 1
65535
65535 2
65533 65536 3 4 5 6 7 8 9 10
'1' (Auto Display
Repeat Enabled)
1st Entire Display Period
2nd Entire Display Period
3rd Entire Display Period
12
65534 1
65535 2
65536
DSPRPT = 0
(Auto Display
Repeat Disabled)
1st Entire
Display Period
OUTn
(GS Data = FFFFh)
OFF
ON
Display period is repeated with
Auto display repeat function.
OUTn is forced off
when BLANK is set to '1'.
Note (1)
(1) OUTn is not turned on until BLANK changes from '1' to '0' or until LAT changes from low to high for a GS data write with TMGRST = 1.
Figure 27. Auto Display Repeat Function
Auto Data Refresh Function
This function allows grayscale (GS) data, dot correction (DC) data, and global brightness control (BC) data to be
input at any time without synchronizing the input to the display timing. If GS, DC, and BC data are sent during a
display period, the input data are held in the first latch for each data register. The data are then transferred to the
second latch when the 65,536th GSCLK occurs. The second latch data are used for the next display period.
Refer to Figure 28 and Figure 29 for the auto data refresh function timing. However, when the BLANK bit in the
first control data latch is set to '1' before the 65,536th GSCLK occurs, the first latch data immediately upload to
the second latch. Also, when a LAT rising edge occurs while the BLANK bit is '1', the selected shift register data
are transferred to the first and second latch at the same time. The data of bits 119-136 (BLANK, DSPRPT,
TMGRST, ESPWM, LODVLT, LSDVLT, LATTMG, IDMENA, IDMRPT, IDMCUR, OLDEN, and PSMODE) in the
control data latch immediately update whenever the data are written into the first latch.
Display Timing Reset Function
The display timing reset function allows initializing the display timing with a LAT rising edge for a GS data write.
This function can be switched on or off with the TMGRST bit in the first control data latch. When the TMGRST bit
is '1', the GS counter is reset to '0' and all outputs are forced off at the LAT rising edge for a GS data write.
Furthermore, the data in the 257-bit common shift register are copied to the first and second GS data latches at
the same time. In addition, the DC and BC data in the first control data latch are transferred to the second data
latch simultaneously. This configuration is identical to the BLANK bit when it changes data from '0' to '1' and '1' to
'0'. Therefore, the BLANK bit is not needed to control the display reset. PWM control resumes from the next
GSCLK rising edge. When the TMGRST bit is '0', the GS counter is not reset and the outputs are not forced off
even with a LAT rising edge.
Copyright © 2012, Texas Instruments Incorporated
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