AM3517_12 Datasheet, PDF (211/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
www.ti.com
SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
6.8 Test Interfaces
The emulation and trace interfaces allow tracing activities of the following CPUs:
• ARM Cortex^TM-A8 through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time
trace of the ARM subsystem operations.
All processors can be emulated via JTAG ports.
6.8.1 Embedded Trace Macro Interface (ETM)
The following tables assume testing over the recommended operating conditions.
Table 6-154. Embedded Trace Macro Interface Switching Characteristics
NO.
PARAMETER
MIN
MAX
f
ETM0
ETM1
ETM2
ETM3
1/t_c(CLK)
t_c(CLK)
t_W(CLK)
t_d(CLK-CTL)
t_d(CLK-D)
Frequency, etk_clk
Cycle time
Clock pulse width, etk_clk
Delay time, etk_clk clock edge to etk_ctl transition
Delay time, etk_clk clock high to etk_d[15:0] transition
166
6.02
3.01
-0.5
0.5
-0.5
0.5
UNIT
MHz
ns
ns
ns
ns
etk_clk
etk_ctl
etk_d[15:0]
ETM2
ETM0
ETM1
ETM3
Figure 6-72. Embedded Trace Macro Interface
ETM3
ETM2
030-110
6.8.2 JTAG Interfaces
AM3517/05 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define
the timing requirements for several tools used to test the AM3517/05 processors as:
• Free running clock tool, like XDS560 and XDS510 tools
• Adaptive clock tool, like RealView ICE tool and Lauterbach tool
6.8.2.1 JTAG Free Running Clock Mode
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-155. JTAG Timing Conditions Free Running Clock Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
C_LOAD
Input signal rise time
Input signal fall time
Output load capacitance
1.8 V
MAX
3.3 V
MAX
5
3
5
3
30
UNIT
ns
ns
pF
Copyright © 2009–2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 211
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