AM3517_12 Datasheet, PDF (148/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
www.ti.com
Table 6-32. DQS and Dx Routing Specification^{(1) (2)}
No. Parameter
1 Center to center DQS-DQSN spacing
2 DQS E differential pair Skew Length Mismatch⁽³⁾
3 Center to center DQS to other DDR2 trace spacing
4 DQS/Dx nominal trace length
5 Dx to DQS Skew Length Mismatch
6 Dx to Dx Skew Length Mismatch
7 Center to center Dx to other DDR2 trace spacing
8 Center to Center Dx to other Dx trace spacing
Min
Typ Max
Unit
2w
25
Mils
4w
DQLM-50 DQLM DQLM+ Mils
50
100
Mils
100
Mils
4w
3w
Notes
See Note ⁽⁴⁾
See Notes ⁽²⁾,
(5)
See Note ⁽⁵⁾
See Note ⁽⁵⁾
See Notes ⁽⁴⁾,
(6)
See Notes ⁽⁷⁾,
(4)
(1) "Dx" indicates a data line. E indicates length of DQS differential pair or Dx signal.
(2) Series terminator, if used, should be located closest to DDR.
(3) Differential impedance should be 100-ohms.
(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(6) Dx's from other DQS domains are considered other DDR2 trace.
(7) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.
Figure 6-30 shows the routing for the SDRC_STRBENx net classes. Table 6-33 contains the routing
specification. SDRC_STRBENx net classes should be shielded from or routed on different layers than the
DQx net classes.
A1
T
T
Microprocessor
A1
Figure 6-30. SDRC_STRBENx Routing
148 Timing Requirements and Switching Characteristics
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