AM3517_12 Datasheet, PDF (157/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
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No.
B2
SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
Table 6-42. McBSP1 Switching Characteristics - Rising Edge and Receive Mode
PARAMETER
td(CLKAE-FSV)
Delay time,
mcbsp1_clkr
active edge to
mcbsp1_fsr /
mcbsp1_fsx
valid
VDDSHV=3.3V
MIN
MAX
0.2
14.8
VDDSHV=1.8V
MIN
MAX
0.2
14.8
UNIT
ns
Table 6-43. McBSP1 Timing Requirements - Rising Edge and Transmit Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B5
tsu(FSXV-
Setup time,
Full Cycle
5.2
4.7
ns
CLKXAE)
mcbsp1_fsx
Slave
valid before
mcbsp1_clkx
active edge
Half Cycle
Slave
4.2
3.7
ns
B6
th(CLKXAE- Hold time,
Full Cycle
5.2
4.7
ns
FSXV)
mcbsp1_fsx
Slave
valid after
mcbsp1_clkx
active edge
Half Cycle
Slave
1.0
0.5
ns
Table 6-44. McBSP1 Switching Characteristics - Rising Edge and Transmit Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B2
td(CLKXAE- Delay time,
FSXV)
mcbsp1_clkx
active edge to
mcbsp1_fsx
valid
0.2
14.8
0.7
14.8
ns
B8
td(CLKXAE- Delay time,
Master
0.6
14.8
0.6
14.8
ns
DXV)
mcbsp1_clkx
active edge to
Slave
0.6
14.8
0.6
14.8
ns
mcbsp1_dx
valid
Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B3
tsu(DRV-
Setup time,
Half Cycle
5.0
5.0
ns
CLKAE)
mcbsp1_dr
Master
valid before
mcbsp1_clkr /
mcbsp1_clkx
Half Cycle
Slave
5.2
5.2
ns
active edge
Full Cycle
4.0
4.0
ns
Master
Full Cycle
4.2
4.2
ns
Slave
B4
th(CLKAE-
Hold time,
Half Cycle
5.8
5.8
ns
DRV)
mcbsp1_dr
Master
valid after
mcbsp1_clkr /
mcbsp1_clkx
Half Cycle
Slave
5.2
5.2
ns
active edge
Full Cycle
1.5
1.5
ns
Master
Full Cycle
0.9
0.9
ns
Slave
B5
tsu(FSV-
Setup time,
Half Cycle
5.2
5.2
ns
CLKAE)
mcbsp1_fsr / Slave
mcbsp1_fsx
valid before
mcbsp1_clkr /
Full Cycle
Slave
4.2
4.2
ns
mcbsp1_clkx
active edge
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Timing Requirements and Switching Characteristics 157
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