AM3517_12 Datasheet, PDF (167/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
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SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
Table 6-76. McBSP4 Switching Characteristics - Rising Edge and Transmit Mode (continued)
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
B8
td(CLKXAE- Delay time,
Master
0.6
16.6
0.6
16.6
ns
DXV)
mcbsp4_clkx
active edge to
Slave
0.6
17.3
0.6
17.3
ns
mcbsp4_dx
valid
Table 6-77. McBSP4 Timing Requirements - Falling Edge and Receive Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B3
tsu(DRV-
Setup time,
Half Cycle
7.5
7.5
ns
CLKXAE)
mcbsp4_dr
Master
valid before
mcbsp4_clkx
active edge
Half Cycle
Slave
7.7
7.7
ns
Full Cycle
5.6
5.6
ns
Master
Full Cycle
5.8
5.8
ns
Slave
B4
th(CLKXAE- Hold time,
Half Cycle
7.7
7.7
ns
DRV)
mcbsp4_dr
Master
valid after
mcbsp4_clkx
active edge
Half Cycle
Slave
5.2
5.2
ns
Full Cycle
1.5
1.5
ns
Master
Full Cycle
0.9
0.9
ns
Slave
B5
tsu(FXSV-
Setup time,
Half Cycle
7.7
7.7
ns
CLKXAE)
mcbsp4_fsx
Slave
valid before
mcbsp4_clkx
active edge
Full Cycle
Slave
5.8
5.8
ns
B6
th(CLKXAE- Hold time,
Half Cycle
5.2
5.2
ns
FSXV)
mcbsp4_fsx
Slave
valid after
mcbsp4_clkx
active edge
Full Cycle
1.0
1.0
ns
Slave
Table 6-78. McBSP4 Switching Characteristics - Falling Edge and Receive Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B2
td(CLKXAE- Delay time, mcbsp4_clkx active 0.2
16.6
0.2
16.6
ns
FSXV)
edge to mcbsp4_fsx valid
Table 6-79. McBSP4 Timing Requirements - Falling Edge and Transmit Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B5
tsu(FSXV-
Setup time,
Half Cycle
7.7
7.7
ns
CLKXAE)
mcbsp4_fsx
Slave
valid before
mcbsp4_clkx
active edge
Full Cycle
Slave
3.7
3.7
ns
B6
th(CLKXAE- Hold time,
Half Cycle
5.2
5.2
ns
FSXV)
mcbsp4_fsx
Slave
valid after
mcbsp4_clkx
active edge
Full Cycle
Slave
1.0
1.0
ns
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Timing Requirements and Switching Characteristics 167
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