AM3517_12 Datasheet, PDF (155/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
www.ti.com
SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
6.6 Serial Communications Interfaces
6.6.1 Multichannel Buffered Serial Port (McBSP) Timing
There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct
serial interface between the AM3517/05 device and other devices in a system such as other application
devices or codecs. It can accommodate a wide range of peripherals and clocked frame-oriented protocols
(I2S, PCM, and TDM) due to its high level of versatility.
The McBSP1-5 modules may support two types of data transfer at the system level:
• The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half-cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time.
The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be
configured accordingly with the external peripheral (activation edge capability) and the type of data
transfer required at the system level.
The AM3517/05 McBSP1-5 timing characteristics are described for both rising and falling activation edges.
McBSP1 supports:
• 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.
• 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are
internally looped back via software configuration, respectively, to the clkr and fsr internal signals for
data receive.
McBSP2, 3, 4, and 5 support only the 4-pin mode.
The following sections describe the timing characteristics for applications in normal mode (that is,
AM3517/05 McBSPx connected to one peripheral) and TDM applications in multipoint mode.
6.6.1.1 McBSP in Normal Mode
The following tables assume=testing over the recommended operating conditions.
Table 6-38. McBSP Timing Conditions
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
Input signal rise time
Input signal fall time
C_LOAD
Output load
capacitance
(1) Maximum value.
1.8V, 3.3 V
VALUE
2 ⁽¹⁾
2
10
UNIT
ns
ns
pF
PARAMETER
tC(CLK)
tW(CLKH)
Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration
Cycle Time,
mcbsp1_clkr/mcbspx_clkx
(1)
Typical pulse duration,
mcbsp1_clkr /
mcbspx_clkx high⁽¹⁾
VDDSHV = 1.8V, 3.3V
MIN
MAX
20.83
0.5*P ⁽²⁾
0.5*P ⁽²⁾
UNIT
ns
ns
(1) In mcbspx, x identifies the McBSP number; 1, 2, 4, or 5.
(2) P = mcbsp1_clkr / mcbspx_clkx clock period.
Copyright © 2009–2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 155
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