AM3517_12 Datasheet, PDF (130/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
www.ti.com
6.4.2.1 LPDDR Interface
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the
need for a complex timing closure process. For more information regarding guidelines for using this
LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification
Application Report (literature number SPRAAV0).
6.4.2.1.1 LPDDR Interface Schematic
Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1
x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is
deleted.
Microprocessor
sdrc_d0
LPDDR
T _DQ0
sdrc_d7
sdrc_dm0
sdrc_dqs0p
sdrc_d8
T _DQ7
T _LDM
T _LDQS
T _DQ8
sdrc_d15
sdrc_dm1
sdrc_dqs1p
sdrc_d16
LPDDR
T _DQ0
T _DQ15
T _UDM
T _UDQS
sdrc_d23
sdrc_dm2
sdrc_dqs2p
sdrc_d24
T _DQ7
T _LDM
T _LDQS
T _DQ8
sdrc_d31
sdrc_dm3
sdrc_dqs3p
sdrc_ba0 ^T
sdrc_ba1 ^T
sdrc_a0 ^T
T _DQ15
T _UDM
T _UDQS
BA0
BA1
A0
BA0
BA1
A0
sdrc_a14 ^T
sdrc_ncs0 ^T
sdrc_ncas ^T
sdrc_nras ^T
sdrc_nwe ^T
sdrc_cke0 ^T
sdrc_clk ^T
sdrc_nclk ^T
A14
CS
CAS
RAS
WE
CKE
CK
CK
A14
CS
CAS
RAS
WE
CKE
CK
CK
Figure 6-17. AM3517/05 LPDDR High Level Schematic (x16 memories)
130 Timing Requirements and Switching Characteristics
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