AM3517_12 Datasheet, PDF (169/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
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SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
6.6.1.1.5 McBSP5
The following tables show the timing conditions and switching characteristics for McBSP5.
Table 6-81. McBSP5 Timing Requirements - Rising Edge and Receive Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B3
tsu(DRV-
Setup time,
Half Cycle
7.5
7.5
ns
CLKXAE)
mcbsp5_dr
Master
valid before
mcbsp5_clkx
active edge
Half Cycle
Slave
7.7
7.7
ns
Full Cycle
5.6
5.6
ns
Master
Full Cycle
5.8
5.8
ns
Slave
B4
th(CLKXAE- Hold time,
Half Cycle
7.5
7.5
ns
DRV)
mcbsp5_dr
Master
valid after
mcbsp5_clkx
active edge
Half Cycle
Slave
7.7
7.7
ns
Full Cycle
1.5
1.5
ns
Master
Full Cycle
0.9
0.9
ns
Slave
B5
tsu(FSV-
Setup time,
Half Cycle
7.7
7.7
ns
CLKXAE)
mcbsp5_fsx
Slave
valid before
mcbsp5_clkx
active edge
Full Cycle
Slave
5.8
5.8
ns
B6
th(CLKXAE- Hold time,
Half Cycle
7.7
7.7
ns
FSV)
mcbsp5_fsx
Slave
valid after
mcbsp5_clkx
active edge
Full Cycle
Slave
1.0
1.0
ns
Table 6-82. McBSP5 Switching Characteristics - Rising Edge and Receive Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B2
td(CLKXAE- Delay time, mcbsp5_clkx active 0.2
14.8
0.7
14.8
ns
FSXV)
edge to mcbsp5_fsx valid
Table 6-83. McBSP5 Timing Requirements - Rising Edge and Transmit Mode
No.
PARAMETER
VDDSHV = 3.3V
VDDSHV = 1.8V
UNIT
MIN
MAX
MIN
MAX
B5
tsu(FSXV-
Setup time,
Half Cycle
7.7
7.7
ns
CLKXAE)
mcbsp5_fsx
Slave
valid before
mcbsp5_clkx
active edge
Full Cycle
Slave
5.8
5.8
ns
B6
th(CLKXAE- Hold time,
Half Cycle
7.7
7.7
ns
FSXV)
mcbsp5_fsx
Slave
valid after
mcbsp5_clkx
active edge
Full Cycle
Slave
1.0
1.0
ns
Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode
No.
PARAMETER
B2
td(CLKXAE- Delay time,
FSXV)
mcbsp5_clkx
active edge to
mcbsp5_fsx
valid
VDDSHV = 3.3V
MIN
MAX
0.2
14.8
VDDSHV = 1.8V
MIN
MAX
0.2
14.8
UNIT
ns
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Timing Requirements and Switching Characteristics 169
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