AM3517_12 Datasheet, PDF (186/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
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6.6.7 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the AM3517/05 and
the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the AM3517/05 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the AM3517/05 device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
6.6.7.1 EMAC Electrical Data/ Timing
The following tables assume testing over the recommended operating conditions.
Table 6-112. RMII Input Timing Requirements
NO.
PARAMETER
fc(REFCLK)
Frequency, REF_CLK
ft (REFCLK)
Frequency stability, REF_CLK
1
tc(REFCLK)
Cycle Time, REF_CLK
2
tw(REFCLKH)
Pulse Width, REF_CLK High
3
tw(REFCLKL)
Pulse Width, REF_CLK Low
6
tsu(RXD-REFCLK)
Input Setup Time, RXD Valid before REF_CLK
High
7
th(REFCLK-RXD)
Input Hold Time, RXD Valid after REF_CLK High
8
tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before
REF_CLK High
9
th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after REF_CLK
High
10
tsu(RXER-REFCLK) Input Setup Time, RXER Valid before REF_CLK
High
11
th(REFCLKR-RXER) Input Hold Time, RXER Valid after REF_CLK
High
1.8V, 3.3V
MIN
TYP
MAX UNIT
50
MHz
+/-50 ppm
20
ns
7
13
ns
7
13
ns
4
ns
2
ns
4
ns
2
ns
4
ns
2
ns
Table 6-113. RMII Timing Conditions
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
Input signal rise time
Input signal fall time
C_LOAD
Output load capacitance
1.8V, 3.3V
MIN
1
1
MAX
5
5
5.5
UNIT
ns
ns
pF
Table 6-114. RMII Output Switching Characteristics
NO.
4
td(REFCLK-TXD)
5
td(REFCLK-TXEN)
PARAMETER
Output Delay Time, REF_CLK High to TXD Valid
Output Delay Time, REF_CLK High to TXEN
Valid
1.8V, 3.3V
MIN
TYP
MAX UNIT
2.5
13
ns
2.5
13
ns
186 Timing Requirements and Switching Characteristics
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