AM3517_12 Datasheet, PDF (139/222 Pages) Texas Instruments – ARM Microprocessors

AM3517, AM3505
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Complete stack up specifications are provided in Table 6-24.
Microprocessor
SDRC_D0
T
SPRS550D – OCTOBER 2009 – REVISED MARCH 2012
DQ0
SDRC_D7
T
SDRC_DM0
T
SDRC_DQS0P ^T
SDRC_DQS0N
T
SDRC_D8
T
DQ7
LDM
LDQS
LDQS#
LQ8
SDRC_D15
T
SDRC_DM1
T
SDRC_DQS1P
T
SDRC_DQS1N
T
SDRC_STRBEN0 ^T
SDRC_STRBEN_DLY0
SDRC_D16
T
Length = avg DQS0-1 length+CLK
x16 DDR2
DQ0
LQ15
UDM
UDQS
UDQS#
SDRC_D23
T
SDRC_DM2
T
SDRC_DQS2P ^T
SDRC_DQS2N
T
SDRC_D24 T
DQ7
LDM
LDQS
LDQS#
DQ8
SDRC_D31
T
SDRC_DM3
T
SDRC_DQS3P ^T
SDRC_DQS3N ^T
SDRC_STRBEN1 ^T
SDRC_STRBEN_DLY1
SDRC_BA0 ^T
SDRC_BA1 T
SDRC_BA2 ^T
SDRC_A0 ^T
Length = avg DQS2-3 length+CLK
DQ15
UDM
UDQS
UDQS#
BA0
BA1
BA2*
A0
BA0
BA1
BA2*
A0
SDRC_A14
SDRC_nCS0
SDRC_nCS1
SDRC_nCAS
SDRC_nRAS
SDRC_nWE
SDRC_nCKE0
SDRC_CLK
SDRC_nCLK
SDRC_ODT
VREFSSTL
DDR_PADREF
T
T
T
T
T
T
T
T
T
T
0.1µF^(A)
0.1µF^(A)
A14*
CS1
CS2*
CAS#
RAS#
WE#
CLK
CLK#
ODT*
VREF
0.1^µF(A)
A14*
CS1
CS2*
CAS#
RAS#
WE#
CLK
CLK#
ODT*
VREF
Vio1.8
0.1µF
1K Ω
1%
0.1µF _{1K Ω}
1%
50 1%
A. See VREF Routing and Topology figure for information on capacitor placement.
Figure 6-23. DDR2 Dual-Memory High Level Schematic
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Timing Requirements and Switching Characteristics 139
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