GC5325SEK Datasheet, PDF (19/24 Pages) Texas Instruments – GC5325 Wideband Digital Predistortion Transmit Processor

GC5325
www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009
LVDS SWITCHING CHARACTERISTICS
Over recommended operating conditions (unless otherwise noted). The following table uses a shorthand nomenclature, NxM.
N means the number of differential pairs used to transmit data from one ADC and M means the number of bits sent serially
down each LVDS pair. Thus, 8x2 means 8 LVDS pairs each containing 2 bits of information sent serially.
PARAMETER
16x1 SDR LVDS MODE ex. ADS5444
f_CLK(ADC)
ADC interface clock frequency
t_su(ADC[#]P)
Input data setup time before CLK↑
t_h(ADC[#]P)
Input data hold time after CLK↑
16x1 DDR LVDS MODE ex. ADS5463
f_CLK(ADC)
ADC interface clock frequency
t_su(ADC[#]P)
Input data setup time before CLK↑↓
t_h(ADC[#]P)
Input data hold time after CLK↑↓
8x2 DDR LVDS MODE ex. ADS5545
f_CLK(ADCA)
t_{su(ADCA[#/2]P)}
t_{h(ADCA[#/2]P)}
f_CLK(ADCB)
t_{su(ADCB[#/2]P)}
t_{h(ADCB[#/2]P)}
ADCA interface clock frequency
Input data setup time before CLK↑↓
Input data hold time after CLK↑↓
ADCB interface clock frequency
Input data setup time before CLK↑↓
Input data hold time after CLK↑↓
TEST CONDITIONS
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
See ⁽¹⁾
See ^{(1) (3)}. For port A
See ^{(1) (3)}. For port A
See ⁽¹⁾
See ^{(1) (4)}. For port B
See ^{(1) (4)}. For port B
MIN TYP MAX UNIT
280 MHz
300
ps
600
ps
100
1200
140 MHz
ps
ps
280 MHz
430
ps
260
ps
280 MHz
800
ps
400
ps
(1) Specifications are limited by GC5325 performance and may exceed the example ADC capabilities for the given interface.
(2) Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (V_OD > 250 mV) to/from ADCCLK and ADCCLKC clock crossing (V_OD =
0).
(3) Setup and hold measured for ADCA[7:0]P, ADCA[7:0]N valid for (V_OD > 250 mV) to/from ADCACLK and ADCACLKC clock crossing
(V_OD = 0).
(4) Setup and hold measured for ADCB[7:0]P, ADCB[7:0]N valid for (V_OD > 250 mV) to/from ADCBCLK and ADCBCLKC clock crossing
(V_OD = 0).
CLK
1/f_CLK(ADC)
CLKC
ADC[15:0]P
ADC[15:0]N
t_su(ADC[#]P)
t_h(ADC[#]P)
T0286-02
Figure 10. LVDS Timing Specifications (16 × 1 SDR LVDS)
CLK
1/f_CLK(ADC)
CLKC
ADC[15:0]P
t_su(ADC[#]P)
ADC[15:0]N
t_h(ADC[#]P)
T0292-01
Figure 11. LVDS Timing Specifications (16 × 1 DDR LVDS)
Copyright © 2009, Texas Instruments Incorporated
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