GC5325SEK Datasheet, PDF (14/24 Pages) Texas Instruments – GC5325 Wideband Digital Predistortion Transmit Processor

GC5325
SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com
GENERAL SWITCHING CHARACTERISTICS
Describes the electrical characteristics for the baseband interface, MFIO, Fast Sync, and MPU interfaces over recommended
operating conditions (unless otherwise noted)
PARAMETER
BASEBAND INTERFACE
f_CLK(BB)
Baseband input clock frequency
t_su(BB)
Input data setup time before BBCLK↑
t_h(BB)
Input data hold time after BBCLK↑
t_{h(SYNCA, -B, -C)}
Duty_CLK(BB)
t_jCLK(BB)
Input data hold time after BBCLK↑
Duty cycle
Baseband input clock cycle-to-cycle jitter⁽¹⁾
TEST CONDITIONS
BB[15:0], BBFR, SYNCA, SYNCB,
and SYNCC; MFIO18/19
BB[15:0], BBFR, SYNCA, SYNCB,
and SYNCC; MFIO18/19
Valid for SYNCA, SYNCB, and
SYNCC
MIN
MAX UNIT
25
1.3
1.5
2
30%
–2.5%
140 MHz
ns
ns
ns
70%
2.5%
(1) Percent of baseband PLL clock period. The baseband PLL clock is typically 2×–4× the baseband clock frequency.
1/f_CLK(BB)
BBCLK
BB[15:0]
t_su(BB)
BBFR
I(ch = 1, t = 1)
Q(ch = 1, t = 1)
t_h(BB)
Q(ch = N, t = 1)
I(ch = 1, t = 2)
Figure 4. Baseband Timing Specifications (ex. Four Interleaved I/Q Channels)
T0284-01
14
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