GC5325SEK Datasheet, PDF (15/24 Pages) Texas Instruments – GC5325 Wideband Digital Predistortion Transmit Processor

GC5325
www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009
Table 12. DPD CLOCK AND FAST SYNC SWITCHING CHARACTERISTICS
f_CLK(DPD)
Duty_CLK(DPD)
t_h(SYNCD)
t_su(SYNCD)
t_{h(SYNCA, -B, -C)}
t_{su(SYNCA, -B, -C)}
t_jCLK(DPD)
PARAMETER
DPD input clock frequency
DPD input clock duty cycle
Input hold time after DPDCLK↑
Input setup time after DPDCLK↑
Input hold time after DPDCLK↑
Input setup time after DPDCLK↑
DPD clock cycle-to-cycle jitter
TEST CONDITIONS
See ⁽¹⁾
See ⁽¹⁾
MIN
100
30%
0.2
0.4
2
0.4
–2.5%
(1) SYNCD is the preferred sync for DPD clock and clock domain.
MAX
280
70%
2.5%
UNIT
MHz
ns
ns
ns
ns
DPDCLK
DPDCLKC
SYNCDC
SYNCD
t_su(SYNCD)
t_h(SYNCD)
SYNCA
SYNCB
SYNCC
t_{su(SYNCA, -B, -C)}
t_{h(SYNCA, -B, -C)}
T0286-01
Figure 5. DPD Clock and Fast Sync Timing Specifications
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