GC5325SEK Datasheet, PDF (10/24 Pages) Texas Instruments – GC5325 Wideband Digital Predistortion Transmit Processor

GC5325
SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com
EM_D[31:0]
EM_A[12:0]
EM_BA[1:0]
EM_CS[2]B
EM_RWB
EM_WEB
C6727 DSP
Asynchronous
Mode
EM_OEB
AXRO[7]
EM_CS[0]B
EM_WE_DQM[3:0]B
EM_CLK
EM_CKE
EM_RASB
EM_CASB
UPDATA[15:0]
UPADDR[9:1]
UPADDR[0]
CEB
GC5325
OEB
WRB
RDB
INTERRUPT
DQ[31:16] / DQ[15:0]¹
A[11:0]
CSB
DQM[3:0]
BA[1:0]
CLK
CKE
SDRAM
1M ´ 16 ´ 4
(64Mb) ´ 2
RASB
CASB
WEB
B0280-02
NOTE: Dual SDRAM modules are used, upper and lower EMIF data lines are split to access each respective memory
module.
Figure 2. DSP to GC5325/SDRAM Interface Specifications
In a typical implementation, the system configuration software resides locally (in nonvolatile memory) to ensure
proper operation at power up. The adaptation algorithm should also reside in the same location; at power up, the
host should transfer/load the software from the nonvolatile memory (FLASH) to the 'C6727 DSP. The size of the
software required to support the GC5325 and 'C6727 should be no more than 128 Mb (16 MB); however, this
allocation is subject to change pending algorithm improvements. The suggested host-to-DSP interface is through
the UHPI port. See Chapter 0.
The port can be configured into multiple modes of data transfer; the Multiplexed Host Address/Data Dual
Halfword Mode is suggested for this application.
Additional specifications and documents for the TMS320C6727 DSP are available from Texas Instruments at:
http://focus.ti.com/docs/prod/folders/print/tms320c6727b.html.
Typical Baseband Interface
The GC5325 baseband interface receives time-interleaved I and Q data for each channel over the 16- or 18-bit
input bus. The BB[15..0] bus is the 16-bit interface or the top 16 bits of the 18-bit interface. The frame strobe
BBFS signal is used to identify the first channel I data. The data is input in channel order, I then Q. The
baseband clock is used to register the interleaved IQ data and frame strobe.
The hardware sync signals SyncA, SyncB, and SyncC are used to time-align internal GC5325 operations. A
0-to-1 transition clocked by BBClock is an active sync signal.
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