GC5325SEK Datasheet, PDF (18/24 Pages) Texas Instruments – GC5325 Wideband Digital Predistortion Transmit Processor

GC5325
SLWS215 – JANUARY 2009 .............................................................................................................................................................................................. www.ti.com
JTAG SWITCHING CHARACTERISTICS
f_TCK
t_p(TCKL)
t_p(TCKH)
t_su(TDI)
t_h(TDI)
t_d(TDO)
PARAMETER
JTAG clock frequency
JTAG clock low period
JTAG clock high period
Input data setup time before TCK↑
Input data hold time after TCK↑
Output data delay from TCK↓
TEST CONDITIONS
Valid for TDI and TMS
Valid for TDI and TMS
MIN
MAX UNIT
50 MHz
10
ns
10
ns
1
ns
6
ns
8 ns
TCK
TDI
TDO
1/f_TCK
t_p(TCKH)
t_p(TCKL)
t_su(TDI)
t_h(TDI)
t_d(TDO)
Figure 8. JTAG Timing Specifications
T0289-01
ELECTRICAL CHARACTERISTICS
TX SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
HSTL MODE – DDR ex. DAC5682
f_CLK(DAC)
DAC output clock frequency
TEST CONDITIONS
R_L = 100 Ω ⁽¹⁾
(1) Because the output clock is DDR, this represents 840 MSPS real or 420 MSPS complex.
DACCLKC
DACCLK
1/f_CLK(DAC)
MIN TYP MAX UNIT
420 MHz
DAC[15:0]P
DAC[15:0]N
I
Q
Figure 9. TX Timing Specifications (HSTL – DDR)
I
T0290-02
18
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