BQ2019PW Datasheet, PDF(19/27 Page) Texas Instruments

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BQ2019PW Datasheet, PDF (19/27 Pages) Texas Instruments – ADVANCED BATTERY MONITORIC

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bq2019

ADVANCED BATTERY MONITOR IC

SLUS465E â DECEMBER 1999 â REVISED FEBRUARY 2003

APPLICATION INFORMATION

clear register (CLR)

The bits in the CLR register (address 0x63) clear the DCR, CCR, SCR, DTC, and CTC registers and reset the

bq2019 by forcing a power-on-reset and setting the state of the STAT pin as described below:

RSVD

POR STAT

CLR BITS

CTC DTC

SCR

CCR

DCR

RSVD

POR

STAT

CTC

DTC

SCR

CCR

DCR

RSVD bit is reserved for future use and should not be modified by the host.

POR bit indicates a power-on-reset has occurred. This bit is set when VCC has gone below

the POR level. This bit can be also set and cleared by the host, but no functions are

affected.

STAT bit (bit 5) sets the state of the open drain output of the STAT pin. A 1 turns off the open

drain output, while a 0 turn the output on. This bit is set to 1 on power-on-reset.

CTC bit (bit 4) clears the CTCH and CTCL registers and the STC bit. A 1 clears the

corresponding registers and bit. After the registers are cleared, the CTC bit is cleared. This

bit is cleared on power-on-reset.

DTC bit (bit 3) clears the DTCH and DTCL registers and the STD bit. A 1 clears the

corresponding registers and bit. After the registers are cleared, the DTC bit is cleared. This

bit is cleared on power-on-reset.

SCR bit (bit 2) clears both the SCRH and SCRL registers. Writing a 1 to this bit clears the

SCRH and SCRL register. After these registers are cleared, the SCR bit is cleared. This bit

is cleared on power-on-reset.

CCR bit (bit 1) clears both the CCRH and CCRL registers Writing a 1 to this bit clears the

CCRH and CCRL registers. After these registers are cleared, the CCR bit is cleared. This

bit is cleared on power-on-reset.

DCR bit (bit 0) clears both the DCRH and DCRL registers to 0. Writing a 1 to this bit clears

the DCRH and DCRL register. Then the DCR bit is cleared. This bit is cleared on

power-on-reset.

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