BQ2019PW Datasheet, PDF (17/27 Pages) Texas Instruments – ADVANCED BATTERY MONITORIC

bq2019
ADVANCED BATTERY MONITOR IC
SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003
APPLICATION INFORMATION
register descriptions (continued)
flash program address register (FPA)
The FPA byte register (address = 0x70) points to the flash address location that is programmed when the
program flash command is issued. This byte is used with the FPD and FCMD register to program an individual
byte in flash memory.
flash program data register (FPD)
The FPD byte register (address = 0x6F) contains the data to be programmed into the flash address location
pointed to by the contents of the FPA register. When the program flash command is issued, the contents of the
FPD register are ANDed with the contents of the byte pointed to by the FPA and then stored into that location.
discharge count registers (DCRH/DCRL)
The DCRH high-byte register (address = 0x6E) and the DCRL low-byte register (address = 0x6D) contain the
count of the discharge and are incremented whenever V_SR < V_SS. These registers continue to count beyond
ffffh, so proper register maintenance by the host system is necessary. The CLR register forces the reset of both
the DCRH and DCRL to zero.
charge count registers (CCRH/CCRL)
The CCRH high-byte register (address = 0x6C) and the CCRL low-byte register (address = 0x6B) contain the
count of the charge, and are incremented whenever V_SR >V_SS. These registers continue to count beyond ffffh,
so proper register maintenance should be done by the host system. The CLR register forces the reset of both
the CCRH and CCRL to zero.
self-discharge count registers (SCRH/SCRL)
The SCRH high-byte register (address = 0x6A) and the SCRL low-byte register (address = 0x69) contain the
self-discharge count. This register is continually updated in both the normal operating and sleep modes of the
bq2019. The counts in these registers are incremented on the basis of time and temperature. The SCR counts
at a rate of 1 count per hour at 20–30°C. The count rate doubles every 10°C up to a maximum of 16 counts/hour
at temperatures above 60°C. The count rate halves every 10°C below 20–30°C to a minimum of 1 count/8 hours
at temperature below 0°C. These registers continue to count beyond ffffh, so proper register maintenance is
required by the host system. The CLR register forces the reset of both the SCRH and SCRL to zero. During
device sleep the bq2019 periodically wakes briefly to maintain the self-discharge registers.
discharge time count registers (DTCH/DTCL)
The DTCH high-byte register (address = 0x68) and the DTCL low-byte register (address = 0x67) determine the
length of time the V_SR < V_SS indicating a discharge. The counts in these registers are incremented at a rate of
4096 counts per hour. If the DTCH/DTCL register continues to count beyond ffffh, the STD bit is set in the
MODE/WOE register, indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.
NOTE:
If a second rollover occurs, STD is cleared. Access to the bq2019 should be timed to clear
DTCH/DTCL more often than every 170 days. The CLR register forces the reset of both the DTCH
and DTCL to zero.
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