BQ2019PW Datasheet, PDF (13/27 Pages) Texas Instruments – ADVANCED BATTERY MONITORIC

bq2019
ADVANCED BATTERY MONITOR IC
SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003
APPLICATION INFORMATION
communicating with the bq2019
The bq2019 includes a single-wire HDQ serial data interface. Host processors, configured for either polled or
interrupt processing, use the interface to access various bq2019 registers. The HDQ pin requires an external
pullup or pulldown resistor. The interface uses a command-based protocol, where the host processor sends a
command byte to the bq2019. The command directs the bq2019 either to store the next eight bits of data
received to a register specified by the command byte or to output the eight bits of data from a register specified
by the command byte. The communication protocol asynchronous return-to-one is referenced to V_SS.
Command and data bytes consist of a stream of eight bits with a maximum transmission rate of 5 Kbits/s. The
least-significant bit of a command or data byte is transmitted first. Data input from the bq2019 may be sampled
using the pulse-width capture timers available on some microcontrollers. A UART can also communicate with
the bq2019. If a communication time-out occurs (for example, if the host waits longer than t_CYCB for the bq2019
to respond or if this is the first access command), then a BREAK should be sent by the host. The host may then
resend the command. The bq2019 detects a BREAK when the HDQ pin is driven to a logic-low state for a time
t_B or greater. The HDQ pin then returns to its normal ready-high logic state for a time t_BR The bq2019 is then
ready for a command from the host processor.
The return-to-one data-bit frame consists of three distinct sections. The first section starts the transmission by
either the host or the bq2019 taking the HDQ pin to a logic-low state for a period t_STRH,B.. The next section is
the actual data transmission, where the data should be valid by a period t_DSU,B, after the negative edge that
starts communication. The data should be held for a period t_∆V /t_∆H to allow the host or bq2019 to sample the
data bit. The final section stops the transmission by returning the HDQ pin to a logic-high state by at least a
period t_SSU,B after the negative edge used to start communication. The final logic-high state should be held until
a period, t_CYCH,B, to allow time to ensure that the bit transmission ceased properly. The serial communication
timing specification and illustration sections give the timings for data and break communication. Communication
with the bq2019 always occurs with the least-significant bit being transmitted first. Figure 3 shows an example
of a communication sequence to read the bq2019 OFR register.
Break
Written By Host to bq2019
LSB
01
CMDR = 73h
2345
MSB
67
Received By Host From bq2019
LSB
01
Data (OFR) = 65h
2345
MSB
67
1 10 0 1 1 1 0
10 100 1 10
MSB
LSB
73h = 0 1 1 1 0 0 1 1
t(RSPS)
MSB
LSB
65h = 0 1 1 0 0 1 0 1
Figure 3. Communication Sequence
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