BQ2019PW Datasheet, PDF (15/27 Pages) Texas Instruments – ADVANCED BATTERY MONITORIC

bq2019
ADVANCED BATTERY MONITOR IC
SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003
APPLICATION INFORMATION
bq2019 registers
register maintenance
The host system is responsible for register maintenance. To facilitate this maintenance, the bq2019 clear
register (TMP/CLR) resets the specific counter or register pair to zero. The host system clears a register by
writing the corresponding register bit to 1. When the bq2019 completes the reset, the corresponding bit in the
TMP/CLR register automatically resets to 0, saving the host an extra write/read cycle. Clearing the DTC register
clears the STD bit and sets the DTC count rate to the default value of 1 count per 0.8789 s. Clearing the CTC
register clears the STC bit and sets the CTC count rate to the default value of 1 count per 0.8789 s.
register map
HDQ
ADDRESS
0x78–0x7F
NAME
IDROM
BIT7
BIT6
0x77
CAL/
COMPEN CALREQ
0x76
0x75
0x74
0x73
0x72
0x71
0x70
0x6F
0x6E
0x6D
0x6C
0x6B
0x6A
0x69
0x68
0x67
0x66
0x65
0x64
0x63
0x62
0x61
0x60
0x40–0x5F
0x20–0x3F
0x00–0x1F
OFFCTM
OFFCTL
—
—
—
FPA
FPD
DCRH
DCRL
CCRH
CCRL
SCRH
SCRL
DTCH
DTCL
CTCH
CTCL
MODE/WOE
CLR
FCMD
TMPH
TMPL
Flash
Flash
RAM/
TVOS
RSVD
DISREG
POR
BIT5 BIT4 BIT3
BIT2
BIT1
BIT0
8 bytes of factory-programmed ROM
CALOK
CHG
OFF
Flash-shadowed VFC offset bits 19–16
Flash-shadowed offset register bits 15–8
Flash-shadowed offset register bits 7–0
Reserved
Reserved
Reserved
Reserved
Program address byte
Flash program data byte
Discharge count register high byte
Discharge count register low byte
Charge count register high byte
Charge count register low byte
Self-discharge count register high byte
Self-discharge count register low byte
Discharge timer counter register high byte
Discharge timer count register low byte
Charge timer counter register high byte
Charge timer counter register low byte
STC STD WOE2 WOE1
WOE0
BIT0
STAT CTC DTC
SCR
CCR
DCR
Flash/control command register
Reserved
TEMP[8]
TEMP[7:0]
PAGE2, 32 bytes of flash
PAGE1, 32 bytes of flash
PAGE0, 32 bytes of flash-shadowed RAM
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