BQ2019PW Datasheet, PDF (18/27 Pages) Texas Instruments – ADVANCED BATTERY MONITORIC

bq2019
ADVANCED BATTERY MONITOR IC
SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003
APPLICATION INFORMATION
register descriptions (continued)
charge-time count registers (CTCH/CTCL)
The CTCH high-byte register (address = 0x66) and the CTCL low-byte register (address = 0x65) determine the
length of time the V_SR >V_SS, indicating a charge activity. The counts in these registers are incremented at a rate
of 4096 counts per hour. If the CTCH/CTCL registers continue to count beyond ffffh, the STC bit is set in the
MODE/WOE register indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.
NOTE:
If a second rollover occurs, STC is cleared. Access to the bq2019 should be timed to clear
CTCH/CTCL more often than every 170 days. The CLR register forces the reset of both the CTCH
and CTCL to zero.
mode, wake-up enable register (MODE/WOE)
As described below, the Mode/WOE register (address = 0x64) contains the offset isolation bit, regulator disable,
the STC and STD bits, and wake-up enable information.
7
TVOS
6
DISREG
MODE/WOE BITS
5
4
3
STC STD WOE2
2
WOE1
1
WOE0
0
BIT0
TVOS
The TVOS bit internally shorts the SR pin to V_SS. This bit is available to optionally isolate
any unwanted residual current (such as bq2019 operational current through the sense
resistor) from the offset current measurements. When the TVOS bit is set to 1, the bq2019
shorts the SR pin to V_SS. When TVOS is 0, the SR pin is not shorted.
NOTE:
TVOS should be set to 0 for normal charge counting operation.
DISREG
DISREG is the disable regulator bit, which turns off the internal operational amplifier used in
the regulator circuit. In applications where the regulator is not used, the DISREG bit can be
set to reduce the bq2019 supply current requirements. A 1 turns off the amplifier, whereas a
0 turns the amplifier on.
STC & STD
The slow time charge (STC) and slow time discharge (STD) flags indicate whether the CTC
or DTC registers have rolled over beyond ffffh. STC set to 1 indicates a CTC rollover; STD
set to 1 indicates a DTC rollover.
WOE[2..0]
The wake-up output enable (WOE) bits (bits 3–1) indicate the voltage level required on the
SR pin so that the bq2019 enters sleep mode after a power-down command is issued.
Whenever |V_SR|<V_WOE, the bq2019 enters sleep mode after either the power-down or the
calibrate and power-down commands have been issued. On bq2019 power-on reset,
these bits are set to 1. Setting all of these bits to zero causes the device to enter sleep
mode, regardless of the SR pin voltage. Refer to Table 3 for the various WOE values.
BIT0
BIT0 is a reserved bit and must always be set to 0. This bit is cleared on power-on-reset.
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