BQ2019PW Datasheet, PDF (16/27 Pages) Texas Instruments – ADVANCED BATTERY MONITORIC

bq2019
ADVANCED BATTERY MONITOR IC
SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003
APPLICATION INFORMATION
register descriptions
IDROM register
The factory programmed 64 bits of ID ROM are located in the eight-byte locations addressed 0x78–0x7f. These
bits can be programmed to a customer’s specification. Contact your Texas Instruments representative for
details.
calibration and offset registers (CAL/OFFCTH, OFFCTM, OFFCTL)
The CAL/OFFCTH register (address 0x77) enables offset compensation, initiates offset calibration, and
indicates that calibration was successful. The register also contains partial-offset correction information. The
OFFCTM, and OFFCTL registers (addresses 0x76 and 0x75) contain the balance of the offset correction
information used during current offset compensation.
7
COMPEN
6
CALREQ
5
CALOK
CAL/OFFCTH
4
3
2
1
0
CHGOFF
Flash-shadowed offset bits 19–16
OFFCTM
7
6
5
4
3
2
1
0
Flash-shadowed offset bits 15–8
OFFCTL
7
6
5
4
3
2
1
0
Flash-shadowed offset bits 7–0
COMPEN
The COMPEN bit enables offset compensation. Offset compensation automatically occurs
when COMPEN is set to 1 and a successful calibration has occurred (CALOK = 0). When
cleared, compensation is disabled. COMPEN is cleared on power-on-reset.
CALREQ
CALREQ bit requests current offset calibration. When this bit is set to 1, the bq2019 waits
for the condition |VSR|< VWOE. When this condition is satisfied, the bq2019 starts
calibration. After calibration is complete, the bq2019 sets the CALOK bit to 0. The CALREQ
bit is cleared on power-on-reset and after a successful calibration.
CALOK
CALOK bit (read-only) indicates that successful offset calibration has been performed. The
CALOK bit is cleared by the bq2019 when the host sets the CALREQ bit. After calibration is
complete, the bq2019 sets the CALOK to 0.
CHGOFF
CHGOFF bit indicates the polarity of the offset. If the CHGOFF bit is set, the measured
offset is positive. The DCR register is incremented if the COMPEN bit is set. If the CHGOFF
bit is cleared, the measured offset is negative and the CCR is incremented If the COMPEN
bit is set.
OFFCT[19..0] The 20 OFFCT bits indicate the time between instances of incrementing a count into either
the CCR or the DCR registers, depending on the state of the CHGOFF. The LSB of this
register is 9.76 ms.
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