BQ2019PW Datasheet, PDF (10/27 Pages) Texas Instruments – ADVANCED BATTERY MONITORIC

bq2019
ADVANCED BATTERY MONITOR IC
SLUS465E – DECEMBER 1999 – REVISED FEBRUARY 2003
APPLICATION INFORMATION
REG output (continued)
current sense offset
calibration
The host enables bq2019 current sense offset calibration by one of two methods. The first method is resetting
the CALREQ bit in the CAL/OFFCTH register to 1. The second method is by issuing the calibrate and
power-down command to the FCMD register. In both cases, when |V_SR|<V_WOE, the bq2019 enters calibration
mode. When calibration is complete, the CALOK bit is set to 0 by the bq2019. The bq2019 performs offset
calibration by measuring the time between two like-polarity VFC pulses and placing this value in the OFFCTH,
OFFCTM, and OFFCTL registers. The LSB of the OFFCTH, OFFCTM, and OFFCTL registers is 9.76 ms. If
polarity of the second pulse received is opposite that of the first pulse received, then calibration resets and
begins again automatically. If during calibrating no pulses occur within 21.3 minutes, or if 21.3 minutes elapse
after the first pulse, then the bq2019 times out and assumes the offset is 4.29 µV.
Any external signal present between SR and V_SS affects the calibration as calculated by the bq2019. The TVOS
bit is optionally available to isolate any unwanted residual current (such as bq2019 operational current through
the sense resistor) from the offset current measurements. This is done by internally shorting the SR pin during
calibration. When the TVOS bit is set to 1, the bq2019 shorts the SR pin to V_SS in response to the value written
to the bit.
compensation
After offset calibration, two methods to compensate for current-sense offset are available. The first method is
to have the bq2019 automatically compensate for current offset. After a successful calibration (i.e., CALOK is
0), the bq2019 automatically compensates for offset when COMPEN bit is set to 1. The bq2019 then periodically
increments either the charge or discharge counter register, depending on the state of the CHGOFF bit. This
period is calculated by multiplying the OFFCTH, OFFCTM, and OFFCTL registers by 9.76 ms.
The second method is for the host to periodically read the OFFCTH, OFFCTM, and OFFCTL registers and
adjust battery capacity.
gas gauge control registers
The host maintains the charge and discharge and the self-discharge count registers (CCR, CTC, DCR, DTC,
and SCR). To facilitate this maintenance, the bq2019 CLR register resets the specific counter or register pair
to zero. The host system clears a register by writing the corresponding register bit to 1. When the bq2019
completes the reset, the corresponding bit in the CLR register is automatically reset to 0. Clearing the DTC or
CTC registers clears the MODE/WOE register bits STC/STD and sets the CTC/DTC count rates to the default
value of 1.138 counts per second.
device temperature measurement
The bq2019 reports die temperature in units of °K in 9 bits through registers TMPL and TMPH[0]. Refer to the
TMP register description for more details.
register interface
Information is exchanged between host system and the bq2019 through the data-register interface (see
Table 4). The register set consists of a 122-location address space of 8-bit bytes segmented into
D 8 bytes of factory-programmed ID ROM
D 32 bytes of flash-shadowed RAM
D 64 bytes of general-purpose flash
D 18 special function registers
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