LMG1205 Datasheet, PDF(17/24 Page) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs

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LMG1205 Datasheet, PDF (17/24 Pages) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs

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10 Layout

LMG1205

SNOSD37 â MARCH 2017

10.1 Layout Guidelines

Small gate capacitance and Miller capacitance enable enhancement mode GaN FETs to operate with fast

switching speed. The induced high dv/dt and di/dt, coupled with a low gate threshold voltage and limited

headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum

performance. Following are some recommendations:

1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and

discharge the GaN FETs gate into a minimal physical area. This decreases the loop inductance and

minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs must be placed close to the

driver.

2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass

capacitor and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the

bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval

and involves high peak current. Minimizing this loop length and area on the circuit board is important to

ensure reliable operation.

3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose

excessive negative voltage transients on the driver. TI recommends connecting the HS pin and VSS pin to

the respective source of the high-side and low-side transistors with a short and low-inductance path.

4. The parasitic source inductance, along with the gate capacitor and the driver pull-down path, can form an

LCR resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to

damp the ringing.

5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the

HB and HS pins to support the high peak current being drawn from VDD during turnon of the FETs. Keeping

bullet #1 (minimized GaN FETs gate driver loop) as the first priority, it is also desirable to place the VDD

decoupling capacitor and the HB to HS bootstrap capacitor on the same side of the PC board as the driver.

The inductance of vias can impose excessive ringing on the IC pins.

6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing low-

ESR ceramic capacitors adjacent to the GaN FETs.

Figure 22 and Figure 23 show recommended layout patterns for the LMG1205. Two cases are considered: (1)

without any gate resistors, and (2) with an optional turnon gate resistor. Note that 0402 surface mount package is

assumed for the passive components in the drawings. For information on DSBGA package assembly, refer to