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LMG1205 Datasheet, PDF (16/24 Pages) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs
LMG1205
SNOSD37 – MARCH 2017
8.2.3 Application Curves
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Conditions:
Input Voltage = 48 V DC, Load Current = 5 A
Traces:
Top Trace: Gate of Low-Side eGaN FET, Volt/div = 2 V
Bottom Trace: LI of LMG1205, Volt/div = 5 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 0.2 µs/div
Figure 20. Low-Side Driver Input and Output
Conditions:
Input Voltage = 48 V DC,
Load Current = 10 A
Traces:
Trace: Switch-Node Voltage, Volts/div = 20 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 50 ns/div
Figure 21. Switch-Node Voltage
9 Power Supply Recommendations
The recommended bias supply voltage range for LMG1205 is from 4.5 V to 5.5 V. The lower end of this range is
governed by the internal UVLO protection feature of the VDD supply circuit. TI recommends keeping proper
margin to allow for transient voltage spikes while not violating the LMG1205 absolute maximum VDD voltage
rating and the GaN transistor gate breakdown voltage limit.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop does not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis
specification, the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on
the VDD power supply output must be smaller than the hysteresis specification of LMG1205 UVLO to avoid
triggering device shutdown.
A local bypass capacitor must be placed between the VDD and VSS pins. This capacitor must be located as
close as possible to the device. TI recommends a low-ESR, ceramic, surface-mount capacitor. TI also
recommends using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high
frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10
μF, for IC bias requirements.
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