LMG1205 Datasheet, PDF (11/24 Pages) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs

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Feature Description (continued)
Table 1. VDD UVLO Feature Logic Operation
CONDITION (V_HB-HS > V_HBR for all cases below)
V_DD - V_SS < V_DDR during device start-up
V_DD - V_SS < V_DDR during device start-up
V_DD - V_SS < V_DDR during device start-up
V_DD - V_SS < V_DDR during device start-up
V_DD - V_SS < V_DDR - V_DDH after device start-up
V_DD - V_SS < V_DDR - V_DDH after device start-up
V_DD - V_SS < V_DDR - V_DDH after device start-up
V_DD - V_SS < V_DDR - V_DDH after device start-up
HI
LI
H
L
L
H
H
H
L
L
H
L
L
H
H
H
L
L
LMG1205
SNOSD37 – MARCH 2017
HO
LO
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Table 2. V_HB-HS UVLO Feature Logic Operation
CONDITION (V_DD > V_DDR for all cases below)
V_HB-HS < V_HBR during device start-up
V_HB-HS < V_HBR during device start-up
V_HB-HS < V_HBR during device start-up
V_HB-HS < V_HBR during device start-up
V_HB-HS < V_HBR - V_HBH after device start-up
V_HB-HS < V_HBR - V_HBH after device start-up
V_HB-HS < V_HBR - V_HBH after device start-up
V_HB-HS < V_HBR - V_HBH after device start-up
HI
LI
H
L
L
H
H
H
L
L
H
L
L
H
H
H
L
L
HO
LO
L
L
L
H
L
H
L
L
L
L
L
H
L
H
L
L
7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
Due to the intrinsic nature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch is
usually higher than a diode forward voltage drop when the gate is pulled low. This causes negative voltage on
HS pin. Moreover, this negative voltage transient may become even more pronounced due to the effects of board
layout and device drain/source parasitic inductances. With high-side driver using the floating bootstrap
configuration, negative HS voltage can lead to an excessive bootstrap voltage, which can damage the high-side
GaN FET. The LMG1205 solves this problem with an internal clamping circuit that prevents the bootstrap voltage
from exceeding 5 V typical.
7.3.4 Level Shift
The level-shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output, which is referenced to the HS pin and
provides excellent delay matching with the low-side driver. Typical delay matching between LO and HO is around
1.5 ns.
7.4 Device Functional Modes
Table 3 shows the device truth table.
Table 3. Truth Table
HI
LI
HOH
HOL
LOH
LOL
L
L
Open
L
Open
L
L
H
Open
L
H
Open
H
L
H
Open
Open
L
H
H
H
Open
H
Open
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