LMG1205 Datasheet, PDF (12/24 Pages) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs

LMG1205
SNOSD37 – MARCH 2017
8 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a
powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor.
Also, gate drivers are indispensable when the outputs of the PWM controller do not meet the voltage or current
levels needed to directly drive the gates of the switching devices. With the advent of digital power, this situation
is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which
cannot effectively turn on a power switch. A level-shift circuit is needed to boost the 3.3 V signal to the gate-drive
voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses.
Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove
inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both
the level-shifting and buffer-drive functions. Gate drivers also address other needs such as minimizing the effect
of high-frequency switching noise (by placing the high-current driver IC physically close to the power switch),
driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and
thermal stress in controllers by moving gate charge power losses from the controller into the driver.
The LMG1205 is a MHz high- and low-side gate driver for enhancement mode GaN FETs in a synchronous
buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a bootstrap technique
and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source
voltage rating of enhancement mode GaN FETs. The LMG1205 has split-gate outputs with strong sink capability,
providing flexibility to adjust the turnon and turnoff strength independently.
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