LMG1205 Datasheet, PDF (10/24 Pages) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs

LMG1205
SNOSD37 – MARCH 2017
7 Detailed Description
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7.1 Overview
The LMG1205 is a high frequency high- and low- side gate driver for enhancement mode Gallium Nitride (GaN)
FETs in a synchronous buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a
bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the
maximum gate-source voltage rating of enhancement mode GaN FETs. The LMG1205 has split-gate outputs
with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently.
The LMG1205 can operate up to several MHz, and is available in a 12-pin DSBGA package that offers a
compact footprint and minimized package inductance.
7.2 Functional Block Diagram
UVLO
& CLAMP
LEVEL
SHIFT
HI
UVLO
LI
HB
HOH
HOL
HS
VDD
LOH
LOL
VSS
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7.3 Feature Description
7.3.1 Input and Output
The input pins of the LMG1205 are independently controlled with TTL input thresholds and can withstand
voltages up to 12 V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs
of an analog PWM controller with up to 12-V power supply, eliminating the need for a buffer stage.
The output pulldown and pullup resistance of LMG1205 is optimized for enhancement mode GaN FETs to
achieve high frequency and efficient operation. The 0.6-Ω pulldown resistance provides a robust low impedance
turnoff path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ω pullup
resistance helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LMG1205
offers flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either the
turnon path and/or the turnoff path.
If the input signal for either of the the two channels, HI or LI, is not used, the control pin must be tied to either
VDD or VSS. These inputs must not be left floating.
7.3.2 Start-up and UVLO
The LMG1205 has an undervoltage lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD
voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs
from being partially turned on. Also, if there is insufficient VDD voltage, the UVLO actively pulls the LOL and HOL
low. When the VDD voltage is above its UVLO threshold, but the HB to HS bootstrap voltage is below the UVLO
threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid
chattering.
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