LMG1205 Datasheet, PDF (14/24 Pages) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs

LMG1205
SNOSD37 – MARCH 2017
www.ti.com
• Q_rr is the reverse recovery charge of the bootstrap diode, which is typically around 4nC
• ΔV is the maximum allowable voltage drop across the bypass capacitor
(1)
TI recommends a 0.1–µF or larger value, good-quality ceramic capacitor. The bypass capacitor must be placed
as close as possible to the device pins to minimize the parasitic inductance.
8.2.2.2 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side switch, DC bias power for HB undervoltage
lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be
calculated with Equation 2.
C_BST ! ^QgH
I_HB u t_ON
'V
Q_rr
where
• I_HB is the quiescent current of the high-side driver
• t_on is the maximum on-time period of the high-side transistor
(2)
A good-quality ceramic capacitor must be used for the bootstrap capacitor. TI recommends placing the bootstrap
capacitor as close as possible to the HB and HS pins.
8.2.2.3 Power Dissipation
The power consumption of the driver is an important measure that determines the maximum achievable
operating frequency of the driver. It must be kept below the maximum power dissipation limit of the package at
the operating temperature. The total power dissipation of the LMG1205 is the sum of the gate driver losses and
the bootstrap diode power loss.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as
P C_LoadH C_LoadL u V_D2D u f_SW
where
• C_LoadH and C_LoadL are the high-side and the low-side capacitive loads, respectively
(3)
It can also be calculated with the total input gate charge of the high-side and the low-side transistors as
P Q_gH Q_gL u V_DD u f_SW
(4)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. Figure 17 shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equations. Figure 17 can be used to
approximate the power losses due to the gate drivers.
Gate driver power dissipation (LO+HO), VDD = 5 V
Figure 17. Neglecting Bootstrap Diode Losses
14
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